Behavioral synthesis of circuits including high impedance buffers

Claim 1

A method for synthesizing circuit structures comprising the steps of: firstly, reducing a series of hardware description language commands to a series of net expressions on a digital computer; secondly, analyzing said series of net expressions for the presence of high impedance states on said digital computer and producing an associated high impedance control expressions when one or ore high impedance states are found; thirdly, synthesizing a circuit specified by said hardware description language commands on said digital computer by utilizing said net expressions and said high impedance control expressions; and fourthly, transforming said synthesized circuit into a plurality of integrated circuit masks for producing integrated circuits embodying the functionality specified by said hardware description language commands.

Claim 2

A method for synthesizing circuit structures comprising the steps of: firstly, reducing a series of hardware description language commands to a series of net expressions on a digital computer; secondly, analyzing said series of net expressions for the presence of high impedance states on said digital computer and producing an associated high impedance control expressions when one or ore high impedance states are found; thirdly, synthesizing a circuit specified by said hardware description language commands on said digital computer by utilizing said net expressions and said high impedance control expressions; and fourthly, transforming said synthesized circuit into a plurality of integrated circuit masks for producing integrated circuits embodying the functionality specified by said hardware description language commands.

Claim 19

A method for creating a high impedance control expressions from a net expression for synthesizing circuit structures comprising the steps of: (a) reducing a series of hardware description language commands to a series of net expressions on a digital computer; (b) setting a high impedance control expression equal to a null using at least one of the following criteria; (i) if a net expression does not include any high impedance operations; (ii) if said net expression is a net only expression; and (iii) if said net expression is a value only net expression without any high impedance states; (c) if said net expression is a value only expression having at least one high impedance state, setting the high impedance control expression to reflect the high impedance state(s) of said net expression; (d) if said net expression contains two or more sub-expressions, repeatedly performing steps (a) and (b) until all sub-expressions in the net expression have been resolved into sub-control expressions to create said high impedance control expression; (e) repeating steps (b) through (d) for each of said series of net expressions to create a series of high impedance control expressions; (f) synthesizing a circuit specified by said hardware description language commands on said digital computer by utilizing said net expressions and said high impedance control expressions; and (g) using said synthesized circuit in the manufacture of an integrated circuit that embodies the functionality specified by said hardware description language commands.

Claim 20

A method for creating a high impedance control expressions from a net expression for synthesizing circuit structures comprising the steps of: (a) reducing a series of hardware description language commands to a series of net expressions on a digital computer; (b) setting a high impedance control expression equal to a null using at least one of the following criteria; (i) if a net expression does not include any high impedance operations; (ii) if said net expression is a net only expression; and (iii) if said net expression is a value only net expression without any high impedance states; (c) if said net expression is a value only expression having at least one high impedance state, setting the high impedance control expression to reflect the high impedance state(s) of said net expression; (d) if said net expression contains two or more sub-expressions, repeatedly performing steps (a) and (b) until all sub-expressions in the net expression have been resolved into sub-control expressions to create said high impedance control expression; (e) repeating steps (b) through (d) for each of said series of net expressions to create a series of high impedance control expressions; (f) synthesizing a circuit specified by said hardware description language commands on said digital computer by utilizing said net expressions and said high impedance control expressions; and (g) using said synthesized circuit in the manufacture of an integrated circuit that embodies the functionality specified by said hardware description language commands.

Claim 25

A method for synthesizing a circuit structure in the manufacture of an integrated circuit described by a collection of one or more hardware description commands, the method comprising the steps of: (1) reducing each hardware description language command to one or more net expressions; (2) selecting one of the net expressions; (3) determining if the selected net expression can produce at least one high impedance state; (4) if the selected net expression cannot produce a high impedance state, assigning a control expression for the selected net expression equal to a null value and returning to step (2); (5) if the selected net expression can produce a high impedance state and the selected net expression is a net only expression, assigning a control expression for the selected net expression equal to a null value and returning to step (2); (6) if the selected net expression has at least one high impedance state and the selected net expression is not a net only expression, determining if the selected net expression is a value only expression; (7) if the selected net expression is a value only expression and does not produce at least one high impedance state, assigning the selected net expression a null value and proceeding to step (2); (8) if the selected net expression is a value only expression and produces at least one high impedance state, manifesting each high impedance state in the selected net expression by inserting a selected bit value at each bit position in the control expression corresponding to a high impedance state that occurs in the selected net expression; (9) if the selected net expression is not a value only net expression, determining that the selected net expressions is a combination of two or more net sub-expressions, decomposing the selected net expression into at least two net sub-expressions, and applying steps (2)-(9) to each sub-expressions; (10) synthesizing a circuit specified by said hardware description language commands on a digital computer by utilizing said net expression and said control expression; and (11) using said synthesized circuit in the manufacture of an integrated circuit that embodies the functionality specified by said hardware description language commands.

Claim 26

A method for synthesizing a circuit structure in the manufacture of an integrated circuit described by a collection of one or more hardware description commands, the method comprising the steps of: (1) reducing each hardware description language command to one or more net expressions; (2) selecting one of the net expressions; (3) determining if the selected net expression can produce at least one high impedance state; (4) if the selected net expression cannot produce a high impedance state, assigning a control expression for the selected net expression equal to a null value and returning to step (2); (5) if the selected net expression can produce a high impedance state and the selected net expression is a net only expression, assigning a control expression for the selected net expression equal to a null value and returning to step (2); (6) if the selected net expression has at least one high impedance state and the selected net expression is not a net only expression, determining if the selected net expression is a value only expression; (7) if the selected net expression is a value only expression and does not produce at least one high impedance state, assigning the selected net expression a null value and proceeding to step (2); (8) if the selected net expression is a value only expression and produces at least one high impedance state, manifesting each high impedance state in the selected net expression by inserting a selected bit value at each bit position in the control expression corresponding to a high impedance state that occurs in the selected net expression; (9) if the selected net expression is not a value only net expression, determining that the selected net expressions is a combination of two or more net sub-expressions, decomposing the selected net expression into at least two net sub-expressions, and applying steps (2)-(9) to each sub-expressions; (10) synthesizing a circuit specified by said hardware description language commands on a digital computer by utilizing said net expression and said control expression; and (11) using said synthesized circuit in the manufacture of an integrated circuit that embodies the functionality specified by said hardware description language commands.