US6240376B1
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Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging
Assignee: Mentor Graphics Corp
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Filing: 1998-07-31
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Granted: 2001-05-29
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Expires: 2018-07-31
Abstract
Abstract Methods of instrumenting synthesizable source code to enable debugging support akin to high-level language programming environments for gate-level simulation are provided. One method of facilitating gate level simulation includes generating cross-reference instrumentation data including instrumentation logic indicative of an execution status of at least one synthesizable register transfer level (RTL) source code statement. A gate-level netlist is synthesized from the source code. Evaluation of the instrumentation logic during simulation of the gate-level netlist facilitates simulation by indicating the execution status of a corresponding source code statement. One method results in a modified gatelevel netlist to generate instrumentation signals corresponding to synthesizable statements within the source code. This may be accomplished by modifying the source code or by generating the modified gate-level netlist as if the source code was modified during synthesis. Alternatively, cross-reference instrumentation data including instrumentation logic can be generated without modifying the gate-level design. The instrumentation logic indicates the execution status of a corresponding cross-referenced synthesizable statement. An execution count of a cross-referenced synthesizable statement can be incremented when the corresponding instrumentation signals indicates the statement is active to determine source code coverage. Source code statements can be highlighted when active for visually tracing execution paths. For breakpoint simulation, a breakpoint can be set at a selected source code statement. The corresponding instrumentation logic from the cross-reference instrumentation data is implemented as a simulation breakpoint. The simulation is halted at a simulation cycle where the values of the instrumentation signals indicate that the source code statement is active.
Inventors
- 👤 Alain Raynaud
- 👤 Luc M. Burgun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:32
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
53 words
A method comprising the steps of: a) identifying at least one statement within a register transfer level (RTL) synthesizable source code; and b) synthesizing the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of the at least one statement.
Claim 2
Independent Claim
53 words
A method comprising the steps of: a) identifying at least one statement within a register transfer level (RTL) synthesizable source code; and b) synthesizing the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of the at least one statement.
Claim 3
Dependent Claim
45 words
The method of claim 1 wherein step b) includes the step of: i) generating instrumentation logic to provide the instrumentation signal as if the source code included a corresponding signal assignment statement within a same executable branch of the source code as the identified statement.
Claim 4
Dependent Claim
52 words
The method of claim 1 wherein step b) includes the steps of: i) initializing a marker to a first value at the beginning of a process within the source code; and ii) setting the marker to a second value within a same executable branch of the source code as the identified statement.
Claim 5
Dependent Claim
27 words
The method of claim 3 further comprising the step of: iii) assigning the value of the marker to the instrumentation signal at the end of the process.
Claim 6
Independent Claim
48 words
A method of generating a gate level design, comprising the steps of: a) creating an instrumentation signal associated with at least one synthesizable statement contained in a register transfer level (RTL) synthesizable source code; and b) synthesizing the source code into a gate-level design having the instrumentation signal.
Claim 7
Independent Claim
48 words
A method of generating a gate level design, comprising the steps of: a) creating an instrumentation signal associated with at least one synthesizable statement contained in a register transfer level (RTL) synthesizable source code; and b) synthesizing the source code into a gate-level design having the instrumentation signal.
Claim 8
Dependent Claim
65 words
The method of claim 5 wherein step a) further comprises the step of: i) inserting a unique variable assignment statement into the source code, wherein the variable assignment statement is adjacent to at least one associated sequential statement; and ii) inserting a unique output signal assignment statement into the source code, wherein the unique output signal is assigned a value associated with the unique variable.
Claim 9
Dependent Claim
37 words
The method of claim 6 wherein the variable is assigned a first value in step a)i), the method further comprising the step of: iii) modifying the source code to initialize the unique variable to a second value.
Claim 10
Dependent Claim
40 words
The method of claim 5 wherein step a) is repeated to create a unique instrumented output signal for each list of sequential statements in the source code, wherein each list corresponds to a synthesizable executable branch of the source code.
Claim 11
Dependent Claim
38 words
The method of claim 5 further comprising the step of: c) generating cross-reference instrumentation data mapping each statement in a selected list to the instrumented output signal associated with that list for every list in the source code.
Claim 12
Dependent Claim
29 words
The method of claim 9 further comprising the steps of: d) simulating the gate level design using at least one of the instrumentation signals to establish a simulation breakpoint.
Claim 13
Dependent Claim
40 words
The method of claim 5 further comprising the steps of: c) displaying the source code, wherein at least one statement within a selected list is highlighted if the instrumentation signal corresponding to the selected list changes to a pre-determined value.
Claim 14
Independent Claim
113 words
A method of generating a gate-level netlist, comprising the steps of: a) receiving register transfer level (RTL) synthesizable source code including synthesizable statements; b) inserting a unique local variable assignment statement into the source code for each branch of code having a list of at least one sequential statement, wherein the unique local variable assignment statement is adjacent to at least one statement within the list; c) inserting a corresponding instrumentation signal assignment statement into the source code for each of the inserted local variables, wherein the instrumentation signal is assigned a value of the corresponding unique local variable; and d) synthesizing the source code into a gate-level design including the instrumentation signals.
Claim 15
Independent Claim
113 words
A method of generating a gate-level netlist, comprising the steps of: a) receiving register transfer level (RTL) synthesizable source code including synthesizable statements; b) inserting a unique local variable assignment statement into the source code for each branch of code having a list of at least one sequential statement, wherein the unique local variable assignment statement is adjacent to at least one statement within the list; c) inserting a corresponding instrumentation signal assignment statement into the source code for each of the inserted local variables, wherein the instrumentation signal is assigned a value of the corresponding unique local variable; and d) synthesizing the source code into a gate-level design including the instrumentation signals.
Claim 16
Dependent Claim
31 words
The method of claim 12 wherein step b) further comprises the steps of: i) assigning each unique local variable a first value; and ii) initializing each local variable with second value.
Claim 17
Dependent Claim
31 words
The method of claim 12 further comprising the step of e) mapping every statement within a selected list to the corresponding instrumentation signal for that selected list as cross-reference instrumentation data.
Claim 18
Dependent Claim
65 words
The method of claim 12 further comprising the steps of: e) setting a breakpoint at a selected statement of the source code; f) identifying the instrumentation signal corresponding to the list associated with the selected statement as a breakpoint signal; and g) simulating the gate-level design, wherein simulation is halted at a simulation cycle that results in the breakpoint signal transitioning to a pre-determined value.
Claim 19
Independent Claim
118 words
A method of generating a gate level netlist, comprising the steps of: a) receiving register transfer level (RTL) synthesizable source code including synthesizable statements; b) modifying the source code to generate a corresponding sampled version of each signal event in a selected process; c) modifying the source code to duplicate the selected process; d) replacing each occurrence of a selected signal event with the corresponding sampled version in the duplicated process; e) replacing each list of sequential statements within an executable branch of the duplicated process with a unique variable assignment statement; f) modifying the duplicated process to include an instrumentation signal assignment for each unique variable; and g) synthesizing the modified source code into a gate-level design.
Claim 20
Independent Claim
118 words
A method of generating a gate level netlist, comprising the steps of: a) receiving register transfer level (RTL) synthesizable source code including synthesizable statements; b) modifying the source code to generate a corresponding sampled version of each signal event in a selected process; c) modifying the source code to duplicate the selected process; d) replacing each occurrence of a selected signal event with the corresponding sampled version in the duplicated process; e) replacing each list of sequential statements within an executable branch of the duplicated process with a unique variable assignment statement; f) modifying the duplicated process to include an instrumentation signal assignment for each unique variable; and g) synthesizing the modified source code into a gate-level design.
Claim 21
Dependent Claim
30 words
The method of claim 16 wherein step e) further comprises the steps of: i) assigning the unique variables a first value; and ii) initializing the unique variables with second value.
Claim 22
Dependent Claim
23 words
The method of claim 16 further comprising the step of e) mapping every statement within each selected list to its corresponding instrumentation signal.
Claim 23
Dependent Claim
67 words
The method of claim 16 further comprising the steps of: h) setting a breakpoint at a selected statement of the source code; i) identifying the instrumentation signal corresponding to the list associated with the selected statement as a breakpoint signal; and j) simulating the gate-level design, wherein simulation is halted at a simulation cycle that results in a transition of the breakpoint signal to a predetermined value.
Claim 24
Independent Claim
90 words
A method of debugging a gate-level design including the steps of: a) setting a breakpoint at a selected statement of a register transfer level (RTL) synthesizable source code; b) inserting a local variable assignment statement adjacent to at least one statement in a list of sequential statements, wherein the list corresponds to an executable branch of the source code including the selected statement; c) modifying the source code to include an instrumentation signal assignment statement for the local variable; and d) generating a gate-level design from the modified source code.
Claim 25
Independent Claim
90 words
A method of debugging a gate-level design including the steps of: a) setting a breakpoint at a selected statement of a register transfer level (RTL) synthesizable source code; b) inserting a local variable assignment statement adjacent to at least one statement in a list of sequential statements, wherein the list corresponds to an executable branch of the source code including the selected statement; c) modifying the source code to include an instrumentation signal assignment statement for the local variable; and d) generating a gate-level design from the modified source code.
Claim 26
Dependent Claim
36 words
The method of claim 20 further comprising the steps of: e) simulating the gate-level design, wherein simulation is halted at a simulation cycle that results in a transition of the instrumentation signal to a pre-determined value.
Claim 27
Dependent Claim
30 words
The method of claim 20 wherein step b) further comprises the steps of: i) assigning the local variable a first value; and ii) initializing the local variable with second value.
Claim 28
Dependent Claim
25 words
The method of claim 20 further comprising the step of e) mapping every statement within the executable branch of source code to the instrumentation signal.
Claim 29
Independent Claim
54 words
A method of simulating a gate-level design comprising the steps of: a) identifying a sensitivity list of a process; b) generating logic to identify signal events for any signal in the sensitivity list; and c) identifying the process as active during simulation when a signal event occurs for any signal in the sensitivity list.
Claim 30
Independent Claim
54 words
A method of simulating a gate-level design comprising the steps of: a) identifying a sensitivity list of a process; b) generating logic to identify signal events for any signal in the sensitivity list; and c) identifying the process as active during simulation when a signal event occurs for any signal in the sensitivity list.
Claim 31
Dependent Claim
25 words
The method of claim 24 wherein step c) further comprises the step of: i) highlighting a source code description of the process displayed during simulation.
Claim 32
Dependent Claim
51 words
The method of claim 24 wherein step b) further comprises the step of: i) sampling each signal in the sensitivity list to generate corresponding instrumented signals; and ii) comparing each signal in the sensitivity list with its corresponding instrumented signal to test each signal in the sensitivity list for an event.
Claim 33
Dependent Claim
29 words
The method of claim 26 wherein step c) further comprises the step of: i) generating an active process output signal defined by logically ORing the results of the comparisons.
Claim 34
Dependent Claim
66 words
A storage medium having stored therein processor executable instructions for generating a gate-level design from a register transfer level (RTL) synthesizable source code, wherein when executed the instructions enable the processor to synthesize the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of at least one synthesizable statement of the source code.
Claim 35
Dependent Claim
66 words
A storage medium having stored therein processor executable instructions for generating a gate-level design from a register transfer level (RTL) synthesizable source code, wherein when executed the instructions enable the processor to synthesize the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of at least one synthesizable statement of the source code.
Claim 36
Dependent Claim
65 words
The storage medium of claim 28 wherein the processor performs the steps of: i) inserting a unique variable assignment statement into the source code, wherein the variable assignment statement is adjacent to at least one associated sequential statement; and ii) inserting a unique output signal assignment statement into the source code, wherein the unique output signal is assigned a value associated with the unique variable.
Claim 37
Dependent Claim
126 words
A storage medium having stored therein processor executable instructions for generating a gate-level design from a register transfer level (RTL) synthesizable source code, wherein when executed the instructions enable the processor to perform the steps of: a) inserting a unique local variable assignment statement into the source code for each branch of code having a list of at least one sequential statement, wherein the unique local variable assignment statement is adjacent to at least one statement within the list; b) inserting a corresponding instrumentation signal assignment statement into the source code for each of the inserted local variables, wherein the instrumentation signal is assigned a value of the corresponding unique local variable; and c) synthesizing the source code into a gate-level design including the instrumentation signals.
Claim 38
Dependent Claim
126 words
A storage medium having stored therein processor executable instructions for generating a gate-level design from a register transfer level (RTL) synthesizable source code, wherein when executed the instructions enable the processor to perform the steps of: a) inserting a unique local variable assignment statement into the source code for each branch of code having a list of at least one sequential statement, wherein the unique local variable assignment statement is adjacent to at least one statement within the list; b) inserting a corresponding instrumentation signal assignment statement into the source code for each of the inserted local variables, wherein the instrumentation signal is assigned a value of the corresponding unique local variable; and c) synthesizing the source code into a gate-level design including the instrumentation signals.
Claim 39
Dependent Claim
33 words
The storage medium of claim 30 having stored therein further instructions to enable the processor to perform the step of: d) mapping every statement within each selected list to its corresponding instrumentation signal.
Claim 40
Dependent Claim
113 words
A storage medium having stored therein processor executable instructions for debugging a gate level design during simulation, wherein when a breakpoint is set at a selected statement of a register transfer level (RTL) synthesizable source code the instructions enable the processor to perform the steps of: a) inserting a local variable assignment statement adjacent to at least one statement in a list of sequential statements within the source code, wherein the list corresponds to an executable branch of the source code including the selected statement; b) modifying the source code to include an instrumentation output signal assignment statement for the local variable; and c) generating a gate-level design from the modified source code.
Claim 41
Dependent Claim
113 words
A storage medium having stored therein processor executable instructions for debugging a gate level design during simulation, wherein when a breakpoint is set at a selected statement of a register transfer level (RTL) synthesizable source code the instructions enable the processor to perform the steps of: a) inserting a local variable assignment statement adjacent to at least one statement in a list of sequential statements within the source code, wherein the list corresponds to an executable branch of the source code including the selected statement; b) modifying the source code to include an instrumentation output signal assignment statement for the local variable; and c) generating a gate-level design from the modified source code.
Claim 42
Dependent Claim
33 words
The storage medium of claim 32 having stored therein further instructions to enable the processor to perform the step of: d) mapping every statement within each selected list to its corresponding instrumentation signal.
References Cited (Backward Citations)
US5623418A
Cited
US5555201A
Cited
US5598344A
Cited
US5870308A
Cited
US5801958A
Cited
US5880971A
Cited
US5553002A
Cited
US5541849A
Cited
US5544067A
Cited
US5220512A
Cited
US5423023A
Cited
US5253255A
Cited
US5325309A
Cited
US5615356A
Cited
US5519627A
Cited
US5461576A
Cited
US5568396A
Cited
US5632032A
Cited
US5758123A
Cited
US5991533A
Cited
US5937190A
Cited
US5513123A
Cited
US5920711A
Cited
US5727187A
Cited
US5841663A
Cited
US5870585A
Cited
US5835380A
Cited
US5768145A
Cited
US6006022A
Cited
US6009256A
Cited
US5960191A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-28 | 2004-11-27 | 2005-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-28 | 2008-11-27 | 2009-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-28 | 2012-11-27 | 2013-05-29 | $7700.00 | Window Closed / Lapsed |