US5991533A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Verification support system
Assignee: Yokogawa Electric Corp
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Filing: 1997-10-10
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Granted: 1999-11-23
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Expires: 2017-10-10
Abstract
Abstract A verification support system having the following characteristics: (1) Before actually making a CPU mounted circuit, virtually make a CPU mounted circuit model and an ICE model and perform verification of the CPU mounted circuit mode with logic simulation, by using the ICE model; (2) When an error is found in the verification of a program using logic simulation, the execution and verification of the steps up to one step before the error point is omitted and execution and verification are performed immediately from the error point, for the purpose of error correction; (3) A waveform obtained as a result of logic simulation and a partially enlarged waveform thereof are displayed on different display regions; (4) A display region for displaying a waveform obtained as a result of logic simulation every hour and a display region for saving a displayed waveform obtained when logic simulation is stopped, are provided separately; (5) When there are a plurality of target logic models, waveforms of logic simulation results are displayed on different display regions, respectively. The stop or restart of the renewing of waveforms can be performed individually or collectively; (6) Before making an actual system by PLC, virtually make a PLC model and a process model and verify the sequence program of the PLC; and (7) Prepare a test program for performing verification when a process model is detached from a PLC model, and verify a sequence program by using a general purpose simulator with a debugging function. The verification system enhances efficiency of development of a CPU mounted circuit, and development of a sequence control system using a PLC.
Inventors
- 👤 Naoki Sano
- 👤 Takeshi Yamamoto
- 👤 Manabu Noriyasu
- 👤 Satoru Natsui
- 👤 Yuji Amano
- 👤 Atsushi Ogasawara
- 👤 Yuko Mizuta
- 👤 Yoko Takihana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:56
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
271 words
A verification support system comprising: a target of verification, comprising a CPU mounted circuit which includes a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and on which peripheral circuitry is mounted around the general purpose CPU; a general purpose CPU model for simulatively executing a function of said general purpose CPU, the general purpose CPU model being stored in said disk and being a file described in hardware description language; a peripheral circuitry model for simulatively executing a function of said peripheral circuitry, the peripheral circuitry model being stored in said disk and being a file described in hardware description language; an ICE model for simulatively executing a function of an ICE, the ICE model being stored in said disk and being a file described in hardware description language; a general purpose logic simulator for receiving therein said general purpose CPU model, said peripheral circuitry model, and said ICE Model, from said disk as input files, and for performing logic simulation of verifying a virtual CPU mounted circuit comprising said general purpose CPU model and said peripheral circuitry model by connecting said ICE model to at least said general purpose CPU model; means for reading display start time and display time width from said disk; display control means for displaying a result of said logic simulation from said display start time and for display time width on a predetermined display region on said CRT display unit; and debugging means for debugging on said predetermined display region.
Claim 2
Dependent Claim
271 words
A verification support system comprising: a target of verification, comprising a CPU mounted circuit which includes a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and on which peripheral circuitry is mounted around the general purpose CPU; a general purpose CPU model for simulatively executing a function of said general purpose CPU, the general purpose CPU model being stored in said disk and being a file described in hardware description language; a peripheral circuitry model for simulatively executing a function of said peripheral circuitry, the peripheral circuitry model being stored in said disk and being a file described in hardware description language; an ICE model for simulatively executing a function of an ICE, the ICE model being stored in said disk and being a file described in hardware description language; a general purpose logic simulator for receiving therein said general purpose CPU model, said peripheral circuitry model, and said ICE Model, from said disk as input files, and for performing logic simulation of verifying a virtual CPU mounted circuit comprising said general purpose CPU model and said peripheral circuitry model by connecting said ICE model to at least said general purpose CPU model; means for reading display start time and display time width from said disk; display control means for displaying a result of said logic simulation from said display start time and for display time width on a predetermined display region on said CRT display unit; and debugging means for debugging on said predetermined display region.
Claim 3
Dependent Claim
302 words
A verification support system which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to the process control unit, a CRT display unit, and a disk for storing a variety of data and programs and which verifies hardware of a target logic by logic simulation, said verification support system further comprising: a target logic mode for simulatively executing a function of said target logic, the target logic model comprising a file which is stored in said disk; a general purpose logic simulator for inputting therein said target logic model, from said disk, as an input file, and for performing verification of hardware of said target logic model by logic simulation; store means for sequentially storing in said disk signal data and simulation time data useful for verification of said target logic model which were obtained as a result of said logic simulation; a time setting file in which a plurality of data for setting display start time and display time width of a result of said simulation, are stored; read means for reading out signal data and simulation time data corresponding to said display start time and said display time width, from said disk, by making reference to the data of display start time and display time width stored in said time setting file; and display means for converting said signal data and simulation time data read out from said disk into a waveform timing diagram and displaying said timing diagram on a plurality to display regions of said CRT display unit, a waveform timing diagram of a predetermined display time width and an enlarged waveform timing diagram of the timing diagram being displayed on different display regions, respectively and waveform timing diagram displayed on each display region being renewed as the logic simulation proceeds.
Claim 4
Dependent Claim
302 words
A verification support system which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to the process control unit, a CRT display unit, and a disk for storing a variety of data and programs and which verifies hardware of a target logic by logic simulation, said verification support system further comprising: a target logic mode for simulatively executing a function of said target logic, the target logic model comprising a file which is stored in said disk; a general purpose logic simulator for inputting therein said target logic model, from said disk, as an input file, and for performing verification of hardware of said target logic model by logic simulation; store means for sequentially storing in said disk signal data and simulation time data useful for verification of said target logic model which were obtained as a result of said logic simulation; a time setting file in which a plurality of data for setting display start time and display time width of a result of said simulation, are stored; read means for reading out signal data and simulation time data corresponding to said display start time and said display time width, from said disk, by making reference to the data of display start time and display time width stored in said time setting file; and display means for converting said signal data and simulation time data read out from said disk into a waveform timing diagram and displaying said timing diagram on a plurality to display regions of said CRT display unit, a waveform timing diagram of a predetermined display time width and an enlarged waveform timing diagram of the timing diagram being displayed on different display regions, respectively and waveform timing diagram displayed on each display region being renewed as the logic simulation proceeds.
Claim 5
Dependent Claim
315 words
A verification support system which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and programs and which verifies hardware of a target logic by logic simulation, said verification support system further comprising: a target logic model for simulatively executing a function of said target logic, the target logic model comprising a file which is stored in said disk; a general purpose logic simulator for inputting therein said target logic model, from said disk, as an input file, and for performing verification of hardware of said target logic model by logic simulation; store means for sequentially storing in said disk signal data and simulation time data desired for verification of said target logic model and which were obtained as a result of said logic simulation; read means for reading out the signal data and simulation time data comprising display start time and display time width from said disk; display means for converting said signal data and said simulation time data read out from said disk into waveform timing diagram starting at said display time and for said time width, for displaying said timing diagram on a first display region of said CRT display unit, and for renewing said timing diagram displayed on said first display region, as said logic simulation proceeds; stop means for stopping logic simulation being executed; waveform save means which, when said logic simulation is stopped causes said read means to read out the signal data and simulation time data stored in said disk immediately before said stop, convert the read out signal data and simulation time data into a waveform timing diagram, and display said timing diagram on a second display region of said CRT display unit; and reopen means for reopening the stopped logic simulation.
Claim 6
Dependent Claim
315 words
A verification support system which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and programs and which verifies hardware of a target logic by logic simulation, said verification support system further comprising: a target logic model for simulatively executing a function of said target logic, the target logic model comprising a file which is stored in said disk; a general purpose logic simulator for inputting therein said target logic model, from said disk, as an input file, and for performing verification of hardware of said target logic model by logic simulation; store means for sequentially storing in said disk signal data and simulation time data desired for verification of said target logic model and which were obtained as a result of said logic simulation; read means for reading out the signal data and simulation time data comprising display start time and display time width from said disk; display means for converting said signal data and said simulation time data read out from said disk into waveform timing diagram starting at said display time and for said time width, for displaying said timing diagram on a first display region of said CRT display unit, and for renewing said timing diagram displayed on said first display region, as said logic simulation proceeds; stop means for stopping logic simulation being executed; waveform save means which, when said logic simulation is stopped causes said read means to read out the signal data and simulation time data stored in said disk immediately before said stop, convert the read out signal data and simulation time data into a waveform timing diagram, and display said timing diagram on a second display region of said CRT display unit; and reopen means for reopening the stopped logic simulation.
Claim 7
Dependent Claim
311 words
A verification support system comprising: a target of verification which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and which comprises a sequence program for operating a PLC of a sequence control system; conversion means for converting said sequence program into a PLC sequence program described in hardware description language; a PLC sequence program file which is stored in said disk and in which the PLC sequence program, converted by said conversion means, is written; an execution model for simulatively executing a function of said PLC, the execution model being stored in said disk and being a file described according to said sequence program in hardware description language; a process model for simulatively executing a function of a control target of said sequence control system, the process model being stored in said disk and being a file described in hardware description language; a test program file which is stored in said disk and in which a test program for verifying said PLC sequence program is written, the test program being described in hardware description language; a general purpose logic simulator for inputting therein said execution model, said process model, said PLC sequence program file, and said test program file, from said disk, as input files, and for performing simulation of verifying by said test program a virtual sequence control system comprising said execution model, said process model, and said PLC sequence program file; means for reading display start time and display time width from said disk; display means for displaying a result of said simulation from said display start time and for display time width on a predetermined display region of said CRT display unit; and debugging means for debugging on said predetermined display region.
Claim 8
Dependent Claim
311 words
A verification support system comprising: a target of verification which comprises a process control unit with a general purpose CPU, a keyboard and a mouse connected to said process control unit, a CRT display unit, and a disk for storing a variety of data and which comprises a sequence program for operating a PLC of a sequence control system; conversion means for converting said sequence program into a PLC sequence program described in hardware description language; a PLC sequence program file which is stored in said disk and in which the PLC sequence program, converted by said conversion means, is written; an execution model for simulatively executing a function of said PLC, the execution model being stored in said disk and being a file described according to said sequence program in hardware description language; a process model for simulatively executing a function of a control target of said sequence control system, the process model being stored in said disk and being a file described in hardware description language; a test program file which is stored in said disk and in which a test program for verifying said PLC sequence program is written, the test program being described in hardware description language; a general purpose logic simulator for inputting therein said execution model, said process model, said PLC sequence program file, and said test program file, from said disk, as input files, and for performing simulation of verifying by said test program a virtual sequence control system comprising said execution model, said process model, and said PLC sequence program file; means for reading display start time and display time width from said disk; display means for displaying a result of said simulation from said display start time and for display time width on a predetermined display region of said CRT display unit; and debugging means for debugging on said predetermined display region.
Claim 9
Dependent Claim
55 words
The system of claim 4, wherein said test program file has written therein a first test program for performing verification when said process is detached from said PLC model, and a second test program for performing verification when said process model is connected to said PLC model, when said virtual sequence control system is verified.
Claim 10
Dependent Claim
37 words
The system of claim 4, further comprising reverse conversion means which, when said PLC sequence program is corrected or changed as a result of verification, converts the corrected or changed PLC sequence program into a sequence program.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-22 | 2003-05-24 | 2003-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-22 | 2007-05-24 | 2007-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-22 | 2011-05-24 | 2011-11-23 | $7700.00 | Window Closed / Lapsed |