US5664159A
Expired / Lapsed
US
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Method for emulating multiple debug breakpoints by page partitioning using a single breakpoint register
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-05-08
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Granted: 1997-09-02
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Expires: 2015-05-08
Abstract
Abstract A single breakpoint address register on a CPU is shared to emulate a plurality of breakpoint registers. A plurality of breakpoints are stored in an emulation area of main memory. One of these breakpoints is loaded into the single breakpoint register on the CPU. When a translation-lookaside buffer (TLB) on the CPU detects a page miss, a page miss handler activates a debug processing routine to determine if the faulting page contains one of the breakpoints. If the faulting page does contain a breakpoint, then this breakpoint is written to the single breakpoint register on the CPU. Any page in TLB is invalidated if it contained the old breakpoint that was overwritten by the new breakpoint in the single breakpoint register. Thus only one breakpoint can have a page translation in the TLB at any time, and the breakpoints are swapped in and out of single breakpoint register when the TLB entries are swapped. A TLB invalidate entry instruction finds the old breakpoint's TLB entry and invalidates it. When multiple breakpoints exist on a single page, then that page is divided into partial pages, with each partial page having just one breakpoint. The TLB entries contain upper and lower bounds fields to identify the extent of the partial page. A bit in the condition register is set when multiple breakpoints exist on the same page.
Inventors
- 👤 David E. Richter
- 👤 James S. Blomgren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:59
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F12/1036
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
261 words
A method for emulating a processor having a plurality of breakpoint register, using a processor with a single breakpoint register for storing just one breakpoint address and a translation-lookaside buffer (TLB) having a plurality of page entries, the breakpoints being addresses which halt execution of a user program when accessed, the method comprising the steps of: freely loading page entries into the TLB when no more than one breakpoint in the plurality of breakpoints is enabled; when two or more breakpoints in the plurality of breakpoints are enabled: signaling a page fault when a faulting page does not have a translation in the TLB; determining if a breakpoint in the plurality of breakpoints falls within the faulting page when the page fault is signaled, the breakpoint falling within the faulting page hereinafter referred to as a first breakpoint; loading a page entry into the TLB for the faulting page; loading the first breakpoint into the breakpoint register on the processor when the faulting page contains the first breakpoint; invalidating any page entries in the TLB other than the faulting page entry for pages containing a breakpoint in the plurality of breakpoints other than the first breakpoint; and halting execution of the user program when the user program accesses an address matching the breakpoint address in the breakpoint register on the processor, wherein only one breakpoint in the plurality of breakpoints has a page translation entry in the TLB, the only one breakpoint being loaded into the breakpoint register on the processor when the faulting page's entry is loaded into the TLB.
Claim 2
Independent Claim
261 words
A method for emulating a processor having a plurality of breakpoint register, using a processor with a single breakpoint register for storing just one breakpoint address and a translation-lookaside buffer (TLB) having a plurality of page entries, the breakpoints being addresses which halt execution of a user program when accessed, the method comprising the steps of: freely loading page entries into the TLB when no more than one breakpoint in the plurality of breakpoints is enabled; when two or more breakpoints in the plurality of breakpoints are enabled: signaling a page fault when a faulting page does not have a translation in the TLB; determining if a breakpoint in the plurality of breakpoints falls within the faulting page when the page fault is signaled, the breakpoint falling within the faulting page hereinafter referred to as a first breakpoint; loading a page entry into the TLB for the faulting page; loading the first breakpoint into the breakpoint register on the processor when the faulting page contains the first breakpoint; invalidating any page entries in the TLB other than the faulting page entry for pages containing a breakpoint in the plurality of breakpoints other than the first breakpoint; and halting execution of the user program when the user program accesses an address matching the breakpoint address in the breakpoint register on the processor, wherein only one breakpoint in the plurality of breakpoints has a page translation entry in the TLB, the only one breakpoint being loaded into the breakpoint register on the processor when the faulting page's entry is loaded into the TLB.
Claim 3
Dependent Claim
59 words
The method of claim 1 wherein the plurality of breakpoints are addresses of data operands, the method further comprising the step of: comparing the breakpoint address in the breakpoint register on the processor to an address of a data operand being accessed by the user program and signaling a breakpoint and halting the user program when a match occurs.
Claim 4
Dependent Claim
57 words
The method of claim 1 wherein the plurality of breakpoints are addresses of instructions, the method further comprising the step of: comparing the breakpoint address in the breakpoint register on the processor to an address of an instruction being fetched for the user program and signaling a breakpoint and halting the user program when a match occurs.
Claim 5
Dependent Claim
113 words
The method of claim 1 further comprising the steps of: determining when more than one breakpoint in the plurality of breakpoints falls within the faulting page; dividing the faulting page into partial pages when more than one breakpoint falls within the faulting page, each partial page containing no more than one breakpoint in the plurality of breakpoints; and loading bounds fields in the TLB when loading the page entry for the faulting page when the faulting page contains more than one breakpoint, the bounds fields defining boundaries of the partial page within the faulting page, whereby pages may contain multiple breakpoints yet the multiple breakpoints share the single breakpoint register on the processor.
Claim 6
Dependent Claim
122 words
The method of claim 4 wherein the step of determining when more than one breakpoint in the plurality of breakpoints falls within the faulting page comprises the steps of: reading a multiple-breakpoint bit in a condition register on the processor, the multiple-breakpoint bit being set when a second breakpoint is enabled in the plurality of breakpoints and the second breakpoint falls within a page which already contains another enabled breakpoint in the plurality of breakpoints; and comparing for a match an address of the faulting page to an address of the page containing the second breakpoint and indicating that more than one breakpoint falls within the faulting page when a match occurs and the multiple-breakpoint bit in the condition register is set.
Claim 7
Dependent Claim
41 words
The method of claim 5 wherein the step of comparing for a match signals a match when an upper portion of the address of the faulting page matches a page address for the address of the page containing the second breakpoint.
Claim 8
Independent Claim
301 words
A system for emulating a processor having a plurality of breakpoint registers, wherein breakpoints are addresses which halt execution of a user program when accessed, the system comprising: a central processing unit (CPU) comprising: a breakpoint register for storing a single breakpoint address which halts execution of a user program when encountered; address compare means, receiving a linear address generated by execution of the user program and coupled to the breakpoint register, for comparing the linear address to the breakpoint address and signaling a breakpoint fault when an address match occurs; a translation-lookaside buffer (TLB), receiving the linear address, the TLB comprising a plurality of page translation entries for pages in memory having a fixed number of offset addresses, each page translation entry comprising a linear address field and a physical address field, the TLB outputting the physical address field for a matching entry when a portion of the linear address matches the linear address field in the matching entry; a memory having a plurality of storage locations addressable by a plurality of physical addresses, the memory having: a first portion for storing a debug table comprising a plurality of debug entries each for storing a breakpoint address; and a second portion for storing an emulation handler routine, the emulation handler routine including: means for copying a breakpoint address from one of the debug entries in the debug table to the breakpoint register on the CPU; invalidation means for invalidating a translation entry in the TLB containing a breakpoint address stored in the debug table but not stored in the breakpoint register on the CPU; wherein only one breakpoint from the debug table in memory has a page translation entry in the TLB, the only one breakpoint being loaded into the breakpoint register on the processor by the emulation handler routine.
Claim 9
Independent Claim
301 words
A system for emulating a processor having a plurality of breakpoint registers, wherein breakpoints are addresses which halt execution of a user program when accessed, the system comprising: a central processing unit (CPU) comprising: a breakpoint register for storing a single breakpoint address which halts execution of a user program when encountered; address compare means, receiving a linear address generated by execution of the user program and coupled to the breakpoint register, for comparing the linear address to the breakpoint address and signaling a breakpoint fault when an address match occurs; a translation-lookaside buffer (TLB), receiving the linear address, the TLB comprising a plurality of page translation entries for pages in memory having a fixed number of offset addresses, each page translation entry comprising a linear address field and a physical address field, the TLB outputting the physical address field for a matching entry when a portion of the linear address matches the linear address field in the matching entry; a memory having a plurality of storage locations addressable by a plurality of physical addresses, the memory having: a first portion for storing a debug table comprising a plurality of debug entries each for storing a breakpoint address; and a second portion for storing an emulation handler routine, the emulation handler routine including: means for copying a breakpoint address from one of the debug entries in the debug table to the breakpoint register on the CPU; invalidation means for invalidating a translation entry in the TLB containing a breakpoint address stored in the debug table but not stored in the breakpoint register on the CPU; wherein only one breakpoint from the debug table in memory has a page translation entry in the TLB, the only one breakpoint being loaded into the breakpoint register on the processor by the emulation handler routine.
Claim 10
Dependent Claim
70 words
The system of claim 7 wherein the CPU further comprises: a bound field in the matching entry in the TLB, the bound field containing a bound for a partial page; bounds checking means, receiving the bound from the matching entry of the TLB, for comparing a portion of the linear address to the bound, signaling a page fault if the linear address is outside the bound for the partial page.
Claim 11
Dependent Claim
48 words
The system of claim 8 wherein the emulation handler routine further comprises: partial page loading means for loading the bound field of the matching entry when the page translation entry is for a page containing multiple breakpoints, the page being divided into partial pages each containing one breakpoint.
Claim 12
Dependent Claim
29 words
The system of claim 7 wherein the breakpoint register stores a single breakpoint address for a data operand and wherein the plurality of breakpoints are breakpoints for data operands.
Claim 13
Dependent Claim
25 words
The system of claim 10 wherein the breakpoint register is a RISC data breakpoint register and wherein the plurality of breakpoints are four CISC breakpoints.
Claim 14
Dependent Claim
30 words
The system of claim 10 wherein the breakpoint register is a RISC data breakpoint register and wherein the plurality of breakpoints are eight CISC breakpoints arranged in two privilege levels.
Claim 15
Dependent Claim
27 words
The system of claim 7 wherein the breakpoint register stores a single breakpoint address for an instruction and wherein the plurality of breakpoints are breakpoints for instructions.
Claim 16
Dependent Claim
25 words
The system of claim 13 wherein the breakpoint register is a RISC instruction breakpoint register and wherein the plurality of breakpoints are four CISC breakpoints.
Claim 17
Dependent Claim
105 words
The system of claim 14 wherein the CPU further comprises: a data breakpoint register for storing a single data breakpoint address which halts execution of a user program when a data operand stored at the single data breakpoint address is accessed; second address compare means, receiving the linear address generated by execution of the user program and coupled to the data breakpoint register, for comparing the linear address to the single data breakpoint address and signaling a data breakpoint fault when an address match occurs; whereby instruction breakpoints are stored in the breakpoint register but data operand breakpoints are stored in the data breakpoint register.
Claim 18
Dependent Claim
27 words
The system of claim 15 wherein the plurality of breakpoints include data operand breakpoints and instruction breakpoints, and wherein the debug table includes data and instruction breakpoints.
Claim 19
Dependent Claim
31 words
The system of claim 7 wherein the first portion of the memory further comprises a valid table for storing valid bits indicting which debug entries in the debug table are enabled.
Claim 20
Independent Claim
205 words
A method for emulating a processor having a plurality of breakpoint registers, using a processor with no breakpoint register and a translation-lookaside buffer (TLB) having a plurality of page entries, the breakpoints being addresses which halt execution of a user program when accessed, the method comprising the steps of: freely loading page entries into the TLB when no breakpoint in the plurality of breakpoints is enabled; when one or more breakpoints in the plurality of breakpoints are enabled: signaling a page fault when a faulting page does not have a translation in the TLB; determining if a breakpoint in the plurality of breakpoints falls within the faulting page when the page fault is signaled, the breakpoint falling within the faulting page hereinafter referred to as a first breakpoint; loading a page entry into the TLB for the faulting page when the faulting page contains no breakpoint; not loading a page entry into the TLB but emulating a memory access for the faulting page when the faulting page contains the first breakpoint; and halting execution of the user program when the user program accesses an address matching the breakpoint address, wherein no breakpoint in the plurality of breakpoints has a page translation entry in the TLB.
Claim 21
Independent Claim
205 words
A method for emulating a processor having a plurality of breakpoint registers, using a processor with no breakpoint register and a translation-lookaside buffer (TLB) having a plurality of page entries, the breakpoints being addresses which halt execution of a user program when accessed, the method comprising the steps of: freely loading page entries into the TLB when no breakpoint in the plurality of breakpoints is enabled; when one or more breakpoints in the plurality of breakpoints are enabled: signaling a page fault when a faulting page does not have a translation in the TLB; determining if a breakpoint in the plurality of breakpoints falls within the faulting page when the page fault is signaled, the breakpoint falling within the faulting page hereinafter referred to as a first breakpoint; loading a page entry into the TLB for the faulting page when the faulting page contains no breakpoint; not loading a page entry into the TLB but emulating a memory access for the faulting page when the faulting page contains the first breakpoint; and halting execution of the user program when the user program accesses an address matching the breakpoint address, wherein no breakpoint in the plurality of breakpoints has a page translation entry in the TLB.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |