Off-chip breakpoint system for a pipelined microprocessor

Claim 2

In a pipelined processor system of a type including an integrated circuit pipelined microprocessor located on a first substrate and an instruction cache and memory management unit (CMMU) located on a second substrate, different from said first substrate, where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced to the pipelined microprocessor in response to the FAULT code reply signal, a breakpoint system for providing a breakpoint exception at a predetermined instruction address, said breakpoint system comprising: at least one breakpoint register for storing a predetermined breakpoint address; means for comparing the code addresses which are sent to the instruction CMMU with said predetermined breakpoint address in said at least one breakpoint register, and for generating a match signal when equivalent addresses are detected; means for providing said match signal to a chip select input on the instruction CMMU; and means coupled to a chip select input on the instruction CMMU, for causing the instruction CMMU to issue the FAULT code reply signal when said match signal is provided to said chip select input, whereby an exception is forced in the pipelined microprocessor.

Claim 3

The breakpoint system of claim 1, wherein the pipelined microprocessor is a Motorola MC88100.

Claim 4

The breakpoint system of claim 2, wherein the instruction CMMU is a Motorola MC88200.

Claim 5

The breakpoint system of claim 2, wherein the instruction CMMU is a Motorola MC88204.

Claim 6

A pipelined processor system having hardware assisted breakpoint capabilities, said system comprising: an integrated circuit pipelined microprocessor of a type which issues a code address and, in response to said code address, receives a code instruction for execution and receives a code reply signal, said pipelined microprocessor being forced to take an exception by a FAULT code reply signal, said integrated circuit pipelined microprocessor located on a first substrate; an instruction cache and memory management unit (CMMU) located on a second substrate, different from said first substrate, said instruction CMMU adapted to receive code addresses from said pipelined microprocessor and to return code instructions to said pipelined microprocessor, said instruction CMMU outputting said FAULT code reply signal in response to a match signal on an instruction CMMU chip select input; at least one breakpoint register for storing a predetermined breakpoint address; comparing means for comparing said code addresses which are sent to said instruction CMMU with said predetermined breakpoint address in said at least one breakpoint register, and for generating said match signal when equivalent addresses are detected; means, coupled to said comparing means, for providing said match signal to said instruction CMMU chip select input; and means for providing said FAULT code reply signal to said pipelined microprocessor.

Claim 7

A pipelined processor system having hardware assisted breakpoint capabilities, said system comprising: an integrated circuit pipelined microprocessor of a type which issues a code address and, in response to said code address, receives a code instruction for execution and receives a code reply signal, said pipelined microprocessor being forced to take an exception by a FAULT code reply signal, said integrated circuit pipelined microprocessor located on a first substrate; an instruction cache and memory management unit (CMMU) located on a second substrate, different from said first substrate, said instruction CMMU adapted to receive code addresses from said pipelined microprocessor and to return code instructions to said pipelined microprocessor, said instruction CMMU outputting said FAULT code reply signal in response to a match signal on an instruction CMMU chip select input; at least one breakpoint register for storing a predetermined breakpoint address; comparing means for comparing said code addresses which are sent to said instruction CMMU with said predetermined breakpoint address in said at least one breakpoint register, and for generating said match signal when equivalent addresses are detected; means, coupled to said comparing means, for providing said match signal to said instruction CMMU chip select input; and means for providing said FAULT code reply signal to said pipelined microprocessor.

Claim 8

The processor system set forth in claim 5, wherein said pipelined microprocessor is a Motorola MC88100.

Claim 9

The processor system set forth in claim 6, wherein said instruction CMMU is a Motorola MC88200.

Claim 10

The processor system set forth in claim 6, wherein said instruction CMMU is a Motorola MC88204.