Microprocessor breakpoint apparatus

Claim 2

A microprocessor device formed in a single substrate, comprising: address means providing a virtual address for referencing an instruction or data; an address bus conveying said virtual address, and a source of bus cycle control information related to said virtual address; address translation means having an input coupled to said address bus and having an output, said address translation means converting said virtual address at said input to a physical address at said output different from said virtual address: a first register for storing a breakpoint address at which a breakpoint is to occur, said breakpoint address being stored in said first register by an instruction referenced using said address means; a second register for storing breakpoint controls defining conditions under which a breakpoint is to occur, said breakpoint controls being stored in said second register by an instruction referenced using said address means, wherein said breakpoint controls include an indication of a data width for said breakpoint address; and breakpoint detecting means responsive to said virtual address on said address bus compared to said breakpoint address of said first register, and responsive to said bus cycle control information compared to said breakpoint controls of said second register, to generate a breakpoint indication responsive to said virtual address and to said bus cycle control information to thereby produce a real time breakpoint operation for said microprocessor device.

Claim 3

A device according to claim 1 wherein said microprocessor device also includes means for receiving an instruction referenced by said address means and for interpreting said instruction, said microprocessor device also includes arithmetic means receiving said data referenced by said address means and operating on said data.

Claim 4

A device according to claim 1 wherein said second register stores breakpoint controls including an indication of whether said virtual address is for an instruction or for data, and an indication of whether said address is for a read or a write operation.

Claim 5

A device according to claim 1 in combination with a memory external to said device and coupled to said output for storing instructions and data referenced by said physical address.

Claim 6

A device according to claim 1 including a plurality of registers for storing breakpoint addresses at which breakpoints are to occur, said first register being one of said plurality of registers.

Claim 7

A device according to claim 1 wherein said breakpoint detecting means includes comparator means for comparing at least portions of said virtual address and said breakpoint address of said first register and means for generating a hit signal if said comparing results in a match.

Claim 8

A device according to claim 6 wherein said breakpoint detecting means includes logic means coupled to said second register and means for generating an enable signal if said bus cycle control information corresponds to said breakpoint controls of said second register, said breakpoint detecting means producing said breakpoint indicating in response to said hit signal and said enable signal.

Claim 11

A method according to claim 8 including the steps of receiving and interpreting said instruction in said microprocessor device, and also receiving and operating on said data in arithmetic means in said microprocessor device in response to said interpreted instruction.

Claim 12

A method according to claim 8 wherein said step of storing in said second register includes storing breakpoint controls including an indication of whether said virtual address is for an instruction or data, and an indicator of whether said address is for a read or a write operation.

Claim 13

A method according to claim 8 including the step of storing instructions and data referenced by said physical address in a memory external to said device and coupled to said output.

Claim 14

A method according to claim 8 including the steps of storing in a plurality of registers breakpoint addresses at which breakpoints are to occur, said first register being one of said plurality of registers.

Claim 15

A method according to claim 8 wherein said step of generating a breakpoint indication includes comparing at least portions of said virtual address with the content of said first register and generating a hit signal if said comparing results in a match.

Claim 16

A method according to claim 13 wherein said step of generating a breakpoint indication includes generating an enable signal if said bus cycle control information corresponds to the content of said second register, and generating said breakpoint indication in response to said hit signal and said enable signal.

Claim 17

A microprocessor device formed in a single substrate, comprising: address means providing a virtual address for referencing an instruction or data; an address bus conveying said virtual address, and a source of bus cycle control information related to said virtual address; address translation means having an input coupled to said address bus and having an output, said address translation means converting said virtual address at said input to a physical address at said output different from said virtual address; a first register for storing a breakpoint address at which a breakpoint is to occur, said breakpoint address being stored in said first register by an instruction referenced using said address means; a second register for storing breakpoint controls defining conditions under which a breakpoint is to occur, said breakpoint controls being stored in said second register by an instruction referenced using said address means, wherein said breakpoint controls include an indication of whether said virtual address is a reference to an instruction or data; and breakpoint detecting means responsive to said virtual address on said address bus compared to said breakpoint address of said first register, and responsive to said bus cycle control information compared to said breakpoint controls of said second register, to generate a breakpoint indication responsive to said virtual address and to said bus cycle control information to thereby produce a real time breakpoint operation for said microprocessor device.

Claim 18

A microprocessor device formed in a single substrate, comprising: address means providing a virtual address for referencing an instruction or data; an address bus conveying said virtual address, and a source of bus cycle control information related to said virtual address; address translation means having an input coupled to said address bus and having an output, said address translation means converting said virtual address at said input to a physical address at said output different from said virtual address; a first register for storing a breakpoint address at which a breakpoint is to occur, said breakpoint address being stored in said first register by an instruction referenced using said address means; a second register for storing breakpoint controls defining conditions under which a breakpoint is to occur, said breakpoint controls being stored in said second register by an instruction referenced using said address means, wherein said breakpoint controls include an indication of whether said virtual address is a reference to an instruction or data; and breakpoint detecting means responsive to said virtual address on said address bus compared to said breakpoint address of said first register, and responsive to said bus cycle control information compared to said breakpoint controls of said second register, to generate a breakpoint indication responsive to said virtual address and to said bus cycle control information to thereby produce a real time breakpoint operation for said microprocessor device.