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US4080650A Expired / Lapsed US ⏱️ 0.0 years remaining

Facilitating return from an on-line debugging program to a target program breakpoint

Assignee: AT&T Inc
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Filing: 1976-07-28
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Granted: 1978-03-21
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Expires: 1996-07-28
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Abstract

Abstract A computer system is disclosed in which a single instruction emulates return of computer control to the point of a program trap without requiring removal of the trap from the program.

Inventors

  • 👤 Jon Terry Beckett

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 02:19
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F11/00; G06F11/36; G06F11/362; G06F11/3648

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 412 words
In an instruction executing computer system having memory means for storing information including a target program of instructions and a debugging program of instructions, a trap instruction having been inserted at a breakpoint location in said target program in place of one word of a selected instruction thereof to transfer control therefrom to said debugging program, said one word and its original address in said target program having been stored elsewhere in said memory means, and said debugging program including a return instruction; an arrangement for returning control of said system from said debugging program to said target program comprising: a plurality of registers; sequence control means coupled to the one of said registers containing an instruction to be executed for selectivey generating a sequence of control signals to control the performance of the set of functions defined by said instruction to be executed; program counter means coupled to said memory means for specifying the location in said memory means from which said information is to be retrieved; retrieval means connected between said memory means and some of said registers, including said one of said registers, and operative in response to certain of said control signals generated by said sequence control means for transferring said information from said location in said memory means sepcified by said program counter means to at least said one of said registers; and gating path means intercoupling said plurality of registers and said program counter means and operative in response to others of said control signals for selectively transferring the contents of said plurality of registers among them and to said program counter means; said sequence control means first operating in response to completion of the performance of the preceding said set of functions, including transfer of said return instruction to said one of said registers, to generate a first sequence of control signals to control performance of the particular set of functions defined by said return instruction, said particular set of functions including operation of said retrieval means and said gating path means to transfer said original address to said program counter means from said memory means and to transfer said one word to said one of said registers from said memory means, and thereafter operating in response to said first sequence of control signals, without first transferring any information from said memory means, to immediately generate a second sequence of control signals to control performance of the set of functions defined by said selected instruction.
Claim 2
Dependent Claim 412 words
In an instruction executing computer system having memory means for storing information including a target program of instructions and a debugging program of instructions, a trap instruction having been inserted at a breakpoint location in said target program in place of one word of a selected instruction thereof to transfer control therefrom to said debugging program, said one word and its original address in said target program having been stored elsewhere in said memory means, and said debugging program including a return instruction; an arrangement for returning control of said system from said debugging program to said target program comprising: a plurality of registers; sequence control means coupled to the one of said registers containing an instruction to be executed for selectivey generating a sequence of control signals to control the performance of the set of functions defined by said instruction to be executed; program counter means coupled to said memory means for specifying the location in said memory means from which said information is to be retrieved; retrieval means connected between said memory means and some of said registers, including said one of said registers, and operative in response to certain of said control signals generated by said sequence control means for transferring said information from said location in said memory means sepcified by said program counter means to at least said one of said registers; and gating path means intercoupling said plurality of registers and said program counter means and operative in response to others of said control signals for selectively transferring the contents of said plurality of registers among them and to said program counter means; said sequence control means first operating in response to completion of the performance of the preceding said set of functions, including transfer of said return instruction to said one of said registers, to generate a first sequence of control signals to control performance of the particular set of functions defined by said return instruction, said particular set of functions including operation of said retrieval means and said gating path means to transfer said original address to said program counter means from said memory means and to transfer said one word to said one of said registers from said memory means, and thereafter operating in response to said first sequence of control signals, without first transferring any information from said memory means, to immediately generate a second sequence of control signals to control performance of the set of functions defined by said selected instruction.
Claim 3
Dependent Claim 82 words
The arrangement in accordance with claim 1 wherein said sequence control means includes: means for generating a predetermined signal in each of said sequence of control signals to indicate the completion of performance of the set of functions defined by any said instruction to be executed other than said return instruction and for omitting the generation of said predetermined signal from said first sequence of control signals that control the performance of said particular set of functions defined by said return instruction.
Claim 4
Dependent Claim 266 words
The arrangement in accordance with claim 2 wherein said control signals are specified by a sequence of micro-instructions executed to perform said set of functions defined by said instruction to be executed, said sequence control means further comprising: an address register coupled to at least said one of said registers to receive a transfer of at least a portion of said instruction to be executed either in response to said predetermined signal in said each said sequence of control signals or to a control signal in said first sequence of control signals that control the performance of said particular set of functions defined by said return instruction; micro-program store means coupled to said address register for storing a plurality of micro-instructions each having a next-address portion and operative to read out one of said micro-instructions from the location in said store means whose address is designated by the contents of said address register; a micro-control instruction register coupled to said store means to receive said one of said micro-instructions read out from said store means and coupled to said address register to transfer thereto the next-address portion of said one of said micro-instructions to thereby designate the address in said store means of the next mirco-instruction to be executed; and means coupled to said micro-control instruction register for decoding said one of said micro-instructions to derive some control signals of said sequence of control signals and coupled to said retrieval means and said gating path means to signal them respectively upon derivation of said certain of said control signals and said others of said control signals.
Claim 5
Dependent Claim 35 words
The arrangement in accordance with claim 1 wherein said memory means comprises read-only memory means having said target program and said trap instruction stored therein and other memory means having said debugging program stored therein.
Claim 6
Independent Claim 98 words
The method of returning control of a computer system to a program wherein one word of a selected multi-word instruction in said program has been replaced with a transfer instruction, said one word and its original address having been saved in memory means of said system; the method comprising the following steps: 1. retrieving said one word and its original address from said memory means and storing them, respectively, in the instruction register and program counter of said computer system, and 2. without further retrieval of information from said memory means, immediately initiating execution of said selected instruction.
Claim 7
Independent Claim 98 words
The method of returning control of a computer system to a program wherein one word of a selected multi-word instruction in said program has been replaced with a transfer instruction, said one word and its original address having been saved in memory means of said system; the method comprising the following steps: 1. retrieving said one word and its original address from said memory means and storing them, respectively, in the instruction register and program counter of said computer system, and 2. without further retrieval of information from said memory means, immediately initiating execution of said selected instruction.
Claim 8
Independent Claim 142 words
The method of returning control of a computer system from a testing program stored in memory means of said computer system to a target program also stored in said memory means and in which a single word breakpoint trap instruction has been inserted in place of the first word of another instruction of said target program, said replaced first word of said other instruction and the address of said breakpoint trap instruction having been stored elsewhere in said memory means; the method comprising the following steps: 1. retrieving said replaced first word of said other instruction and said address of said breakpoint trap instruction from said memory means and storing them, respectively, in instruction register means and program counter means of said computer system, and 2. without further retrieval of information from said memory means, immediately initiating execution of said other instruction.
Claim 9
Independent Claim 142 words
The method of returning control of a computer system from a testing program stored in memory means of said computer system to a target program also stored in said memory means and in which a single word breakpoint trap instruction has been inserted in place of the first word of another instruction of said target program, said replaced first word of said other instruction and the address of said breakpoint trap instruction having been stored elsewhere in said memory means; the method comprising the following steps: 1. retrieving said replaced first word of said other instruction and said address of said breakpoint trap instruction from said memory means and storing them, respectively, in instruction register means and program counter means of said computer system, and 2. without further retrieval of information from said memory means, immediately initiating execution of said other instruction.
Claim 10
Dependent Claim 186 words
The method of claim 6 wherein said step 1 comprises the following steps: a. adjusting said program counter means to specify the address of the location in said memory means in which said address of said breakpoint trap instruction is stored in accordance with address information specified by a return instruction previously stored in said instruction register means; b. retrieving said address of said breakpoint trap instruction from the location in said memory means whose address is specified by said program counter means and storing said address of said breakpoint trap instruction in a first register of said computer system; c. readjusting said program counter means to specify the address of the location in said memory means in which said first word of said other instruction is stored; d. retrieving said first word of said other instruction from the location in said memory means whose address is specified by said program counter means and storing said first word of said other instruction in said instruction register means; and e. gating said address of said breakpoint trap instruction from said first register to said program counter means.

References Cited (Backward Citations)

US3292155A Cited
US3593297A Cited
US3696340A Cited
US3909802A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-03-20 1981-09-19 1982-03-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-03-20 1985-09-19 1986-03-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-03-20 1989-09-19 1990-03-21 $7700.00 Window Closed / Lapsed

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