US5249278A
Expired / Lapsed
US
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Microprocessor breakpoint apparatus
Assignee: Intel Corp
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Filing: 1992-08-21
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Granted: 1993-09-28
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Expires: 2012-08-21
Abstract
Abstract A breakpoint apparatus incorporated in a single chip microprocessor. The apparatus permits breakpoints on specific references to either program instructions or data. The width of the breakpoint address can be varied, the apparatus includes a logic circuit for determining if the reference represented by the breakpoint address overlaps the current virtual address.
Inventors
- 👤 Joseph C. Krauskopf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
283 words
In an integrated circuit microprocessor which includes address generation circuitry for generating virtual addresses for reference to program instructions and data, address translation circuitry for converting said virtual addresses to physical addresses, an interpretation unit for interpreting program instructions, and an arithmetic unit for operating upon data in accordance with interpreted instructions, an improvement for providing a breakpoint signal comprising: a first register for storing a virtual address, which determines where a breakpoint is to occur, said virtual address hereinafter referred to as a breakpoint address, said first register being loaded using a predetermined instruction interpreted by said interpretation unit; a second register for storing control bits, which determine conditions when said breakpoint is to occur, said second register being loaded using a predetermined instruction interpreted by said interpretation unit; and breakpoint circuitry for generating said breakpoint signal, said breakpoint circuitry comparing at least a portion of said breakpoint address from said first register with at least a portion of a current virtual address, said breakpoint circuitry coupled to said second register to sense at least one of said stored control bits which determines if a breakpoint is to occur when said current virtual address is a reference to data or to program instructions, said breakpoint circuitry also coupled to receive bus control signals providing an identification of whether said current virtual address is a reference to data or to program instructions, said breakpoint circuitry generating said breakpoint signal when said current virtual address is an address where a breakpoint is to occur and when said at least one of said control bits matches said indentification; said first and second registers and breakpoint circuitry providing a real time breakpoint signal to said microprocessor.
Claim 2
Dependent Claim
283 words
In an integrated circuit microprocessor which includes address generation circuitry for generating virtual addresses for reference to program instructions and data, address translation circuitry for converting said virtual addresses to physical addresses, an interpretation unit for interpreting program instructions, and an arithmetic unit for operating upon data in accordance with interpreted instructions, an improvement for providing a breakpoint signal comprising: a first register for storing a virtual address, which determines where a breakpoint is to occur, said virtual address hereinafter referred to as a breakpoint address, said first register being loaded using a predetermined instruction interpreted by said interpretation unit; a second register for storing control bits, which determine conditions when said breakpoint is to occur, said second register being loaded using a predetermined instruction interpreted by said interpretation unit; and breakpoint circuitry for generating said breakpoint signal, said breakpoint circuitry comparing at least a portion of said breakpoint address from said first register with at least a portion of a current virtual address, said breakpoint circuitry coupled to said second register to sense at least one of said stored control bits which determines if a breakpoint is to occur when said current virtual address is a reference to data or to program instructions, said breakpoint circuitry also coupled to receive bus control signals providing an identification of whether said current virtual address is a reference to data or to program instructions, said breakpoint circuitry generating said breakpoint signal when said current virtual address is an address where a breakpoint is to occur and when said at least one of said control bits matches said indentification; said first and second registers and breakpoint circuitry providing a real time breakpoint signal to said microprocessor.
Claim 3
Dependent Claim
24 words
The improvement according to claim 1 wherein said second register stores control bits including an indication of a data width for said breakpoint address.
Claim 4
Dependent Claim
39 words
The improvement according to claim 1 wherein said second register stores control bits including an indication of whether a breakpoint is to occur on a reference to data during a read cycle only or a read or write cycle.
Claim 5
Dependent Claim
27 words
The improvement according to claim 1 in combination with a memory external to said microprocessor, said memory for storing instructions and data referenced by said physical address.
Claim 6
Dependent Claim
31 words
The improvement according to claim 1 including a plurality of registers for storing breakpoint addresses at which breakpoints are to occur, said first register being one of said plurality of registers.
Claim 7
Dependent Claim
279 words
In an integrated circuit microprocessor which includes address generation circuitry for generating virtual addresses for reference to program instructions and data, address translation circuitry for converting said virtual addresses to physical addresses, an interpretation unit for interpreting program instructions, and an arithmetic unit for operating upon data in accordance with interpreted instructions, a process for providing a real time breakpoint signal to said microprocessor, said process comprising the steps of: providing a first register for storing a virtual address where a breakpoint is to occur, said virtual address hereinafter referred to as a breakpoint address, said first register being loaded using a predetermined instruction interpreted by said interpretation unit; providing a second register for storing control bits defining conditions when a breakpoint is to occur, said control bits defining if a breakpoint is to occur when said breakpoint address is a reference to data or to program instructions, said second register being loaded using a predetermined instruction interpreted by said interpretation unit; receiving a current virtual address; receiving a bus control signal indicating whether said current virtual address is a reference to data or to program instructions; comparing at least a portion of said breakpoint address from said first register with at least a portion of said current virtual address; comparing at least a portion of said control bits from said second register with said bus control signal; and generating said breakpoint signal when, i) said at least a portion of said breakpoint address from said first register matches said at least a portion of said current virtual address, and ii) said at least a portion of said control bits from said second register matches said bus control signal.
Claim 8
Dependent Claim
279 words
In an integrated circuit microprocessor which includes address generation circuitry for generating virtual addresses for reference to program instructions and data, address translation circuitry for converting said virtual addresses to physical addresses, an interpretation unit for interpreting program instructions, and an arithmetic unit for operating upon data in accordance with interpreted instructions, a process for providing a real time breakpoint signal to said microprocessor, said process comprising the steps of: providing a first register for storing a virtual address where a breakpoint is to occur, said virtual address hereinafter referred to as a breakpoint address, said first register being loaded using a predetermined instruction interpreted by said interpretation unit; providing a second register for storing control bits defining conditions when a breakpoint is to occur, said control bits defining if a breakpoint is to occur when said breakpoint address is a reference to data or to program instructions, said second register being loaded using a predetermined instruction interpreted by said interpretation unit; receiving a current virtual address; receiving a bus control signal indicating whether said current virtual address is a reference to data or to program instructions; comparing at least a portion of said breakpoint address from said first register with at least a portion of said current virtual address; comparing at least a portion of said control bits from said second register with said bus control signal; and generating said breakpoint signal when, i) said at least a portion of said breakpoint address from said first register matches said at least a portion of said current virtual address, and ii) said at least a portion of said control bits from said second register matches said bus control signal.
Claim 9
Dependent Claim
24 words
The process according to claim 6 wherein said second register stores control bits including an indication of a data width for said breakpoint address.
Claim 10
Dependent Claim
39 words
The process according to claim 6 wherein said second register stores control bits including an indication of whether a breakpoint is to occur on a reference to data during a read cycle only or a read or write cycle.
Claim 11
Dependent Claim
24 words
The process according to claim 6 wherein instructions and data referenced by said physical address are stored in a memory external to said microprocessor.
Claim 12
Dependent Claim
29 words
The process according to claim 6 further including a step of providing a second register for storing a different breakpoint address at which a different breakpoint is to occur.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-27 | 2005-03-29 | 2005-09-28 | $7700.00 | Window Closed / Lapsed |