Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip

Claim 1

An apparatus for testing the operation of an integrated circuit chip, said chip having internal test points which produce parallel data, comprising: shift register means (8) for taking a snapshot of an internal state of said integrated circuit chip at a desired clock cycle by loading said shift register in parallel with said parallel data from said internal test points; said shift register having a serial output (19); control logic means (14) connected to said shift register means (8) for shifting said data out of said shift register serially at said serial output (19), one bit per clock cycle; and, tester means (16) connected to said serial output (19) of said shift register means (8) for displaying said data in a useable form on a computer display; said tester means including a SCAN# signal means (40) connected to said control logic means (14) for placing said control logic (14) in a debug mode or a production testing mode, depending upon the state of said SCAN# signal means (40).

Claim 2

An apparatus for testing the operation of an integrated circuit chip, said chip having internal test points which produce parallel data, comprising: shift register means (8) for taking a snapshot of an internal state of said integrated circuit chip at a desired clock cycle by loading said shift register in parallel with said parallel data from said internal test points; said shift register having a serial output (19); control logic means (14) connected to said shift register means (8) for shifting said data out of said shift register serially at said serial output (19), one bit per clock cycle; and, tester means (16) connected to said serial output (19) of said shift register means (8) for displaying said data in a useable form on a computer display; said tester means including a SCAN# signal means (40) connected to said control logic means (14) for placing said control logic (14) in a debug mode or a production testing mode, depending upon the state of said SCAN# signal means (40).

Claim 4

The method of testing the operation of logic on an integrated circuit chip in either a debug mode or a test mode depending upon the state of a SCAN# signal being in a first state or a second state, respectively, said chip having internal test points which produce parallel data, comprising the steps of: (a) placing said SCAN# signal in said first state to activate said debug mode; (b) taking a first snapshot of a first internal state of said chip at a first clock cycle by loading a shift register in parallel with said parallel data from said internal test points at a first clock cycle capture point; (c) shifting said data out of said shift register serially at a serial output of said shift register, one bit per clock cycle; (d) displaying said data in a useable form on a computer display; (e) taking a second snapshot of a second internal state of said chip at a second clock cycle, said second clock cycle being one clock cycle later than said first clock cycle capture point.

Claim 5

The method of testing the operation of logic on an integrated circuit chip in either a debug mode or a test mode depending upon the state of a SCAN# signal being in a first state or a second state, respectively, said chip having internal test points which produce parallel data, comprising the steps of: (a) placing said SCAN# signal in said first state to activate said debug mode; (b) taking a first snapshot of a first internal state of said chip at a first clock cycle by loading a shift register in parallel with said parallel data from said internal test points at a first clock cycle capture point; (c) shifting said data out of said shift register serially at a serial output of said shift register, one bit per clock cycle; (d) displaying said data in a useable form on a computer display; (e) taking a second snapshot of a second internal state of said chip at a second clock cycle, said second clock cycle being one clock cycle later than said first clock cycle capture point.

Claim 6

The method of testing the operation of logic on an integrated circuit chip in either a debug mode or a test mode depending upon the state of a SCAN# signal being in a first state or a second state, respectively, said chip having internal test points which produce parallel data, comprising the steps of: (a) placing said SCAN# signal in said first state to activate said debug mode; (b) taking a first snapshot of a first internal state of said chip at a first clock cycle by loading a shift register in parallel with said parallel data from said internal test points at a first clock cycle capture point; (c) shifting said data out of said shift register serially at a serial output of said shift register, one bit per clock cycle; (d) displaying said data in a useable form on a computer display; (e) taking a second snapshot of a second internal state of said chip at a second clock cycle, said second clock cycle being one clock cycle later than said first clock cycle capture point; (f) placing said SCAN# signal in said second state to activate said test mode; (g) exercising said logic with a simulated input; (h) exclusive ORing said parallel data with a previous contents of said shift register; (i) shifting said result by one bit position; and, (j) comparing said output with said simulated input.

Claim 7

The method of testing the operation of logic on an integrated circuit chip in either a debug mode or a test mode depending upon the state of a SCAN# signal being in a first state or a second state, respectively, said chip having internal test points which produce parallel data, comprising the steps of: (a) placing said SCAN# signal in said first state to activate said debug mode; (b) taking a first snapshot of a first internal state of said chip at a first clock cycle by loading a shift register in parallel with said parallel data from said internal test points at a first clock cycle capture point; (c) shifting said data out of said shift register serially at a serial output of said shift register, one bit per clock cycle; (d) displaying said data in a useable form on a computer display; (e) taking a second snapshot of a second internal state of said chip at a second clock cycle, said second clock cycle being one clock cycle later than said first clock cycle capture point; (f) placing said SCAN# signal in said second state to activate said test mode; (g) exercising said logic with a simulated input; (h) exclusive ORing said parallel data with a previous contents of said shift register; (i) shifting said result by one bit position; and, (j) comparing said output with said simulated input.

Claim 8

The method of testing the operation of an integrated circuit chip in a debug mode or a production testing mode, said chip having internal test points which produce parallel data, comprising the steps of: (a) asserting a SCAN# (40) input low, which determines whether a shift register performs a latch-then-scan function, as required by said debug mode, or whether it does a compression-and-shift on parallel inputs to said shift register, as needed by said production testing mode; (b) loading said parallel data into said register in a first clock cycle subsequent to said SCAN# being asserted low to thereby capture first parallel data in said shift register; (c) shifting said first parallel data serially one bit position towards a serial output of said shift register in a next clock cycle; (d) repeating step (d) during each subsequent clock cycle that said SCAN# signal input is held asserted low; (e) shifting said register one more time in the first clock cycle that SCAN# is asserted high again; and, (f) repeating steps (a) through (e) at chosen successive points in time.

Claim 9

The method of testing the operation of an integrated circuit chip in a debug mode or a production testing mode, said chip having internal test points which produce parallel data, comprising the steps of: (a) asserting a SCAN# (40) input low, which determines whether a shift register performs a latch-then-scan function, as required by said debug mode, or whether it does a compression-and-shift on parallel inputs to said shift register, as needed by said production testing mode; (b) loading said parallel data into said register in a first clock cycle subsequent to said SCAN# being asserted low to thereby capture first parallel data in said shift register; (c) shifting said first parallel data serially one bit position towards a serial output of said shift register in a next clock cycle; (d) repeating step (d) during each subsequent clock cycle that said SCAN# signal input is held asserted low; (e) shifting said register one more time in the first clock cycle that SCAN# is asserted high again; and, (f) repeating steps (a) through (e) at chosen successive points in time.

Claim 11

An apparatus for testing the operation of an integrated circuit chip, said chip having internal test points which produce parallel data, comprising: a shift register (8) for taking a snapshot of an internal state of said integrated circuit chip at a desired clock cycle by loading said shift register in parallel with said parallel data from said internal test points; said shift register having a serial output (19); a control logic (14) connected to said shift register (8) for shifting said data out of said shift register serially at said serial output (19), one bit per clock cycle; and, a tester (16) connected to said serial output (19) of said shift register (8) for displaying said data in a useable form on a computer display; said tester including a SCAN# signal (40) connected to said control logic (14) for placing said control logic (14) in a debug mode or a production testing mode, depending upon the state of said SCAN# signal (40).

Claim 12

An apparatus for testing the operation of an integrated circuit chip, said chip having internal test points which produce parallel data, comprising: a shift register (8) for taking a snapshot of an internal state of said integrated circuit chip at a desired clock cycle by loading said shift register in parallel with said parallel data from said internal test points; said shift register having a serial output (19); a control logic (14) connected to said shift register (8) for shifting said data out of said shift register serially at said serial output (19), one bit per clock cycle; and, a tester (16) connected to said serial output (19) of said shift register (8) for displaying said data in a useable form on a computer display; said tester including a SCAN# signal (40) connected to said control logic (14) for placing said control logic (14) in a debug mode or a production testing mode, depending upon the state of said SCAN# signal (40).