US6952032B2 — Programmable array logic or memory devices with a…

Claim 1

Independent Claim 163 words

A flash memory array, comprising: a number of depletion mode, non-volatile memory cells, wherein each non-volatile memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed which produce different barrier heights at an interface with the floating gate and control gate; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the flash memory array; a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the flash memory array.

Claim 2

Dependent Claim 163 words

A flash memory array, comprising: a number of depletion mode, non-volatile memory cells, wherein each non-volatile memory cell includes: a first source/drain region and a second source/drain region separated by a channel region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed which produce different barrier heights at an interface with the floating gate and control gate; a number of sourcelines coupled to the first source/drain regions along a first selected direction in the flash memory array; a number of control gate lines coupled to the control gates along a second selected direction in the flash memory array; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the flash memory array.

Claim 3

Dependent Claim 65 words

The flash memory array of claim 1 , wherein the asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 4

Dependent Claim 33 words

The flash memory array of claim 1 , wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator.

Claim 5

Dependent Claim 62 words

The flash memory array of claim 3 , wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate.

Claim 6

Dependent Claim 55 words

The flash memory array of claim 4 , wherein the metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

Claim 7

Dependent Claim 42 words

The flash memory array of claim 1 , wherein the second selected direction and the third selected direction are parallel to one another and orthogonal to the first selected direction, and wherein the number of control gate lines serve as address lines.

Claim 8

Dependent Claim 42 words

The flash memory array of claim 1 , wherein the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction, and wherein the number of control gate lines serve as address lines.

Claim 9

Dependent Claim 40 words

The flash memory array of claim 1 , wherein the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction, and wherein the number of bitlines serve as address lines.

Claim 10

Dependent Claim 191 words

An array of flash memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.

Claim 11

Dependent Claim 191 words

An array of flash memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells.

Claim 12

Dependent Claim 66 words

The array of flash memory cells of claim 9 , wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , Zro 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 13

Dependent Claim 35 words

The array of flash memory cells of claim 9 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator.

Claim 14

Dependent Claim 63 words

The array of flash memory cells of claim 11 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate.

Claim 15

Dependent Claim 55 words

The flash memory array of claim 12 , wherein the metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

Claim 16

Dependent Claim 53 words

The array of flash memory cells of claim 9 , wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 17

Dependent Claim 68 words

The array of flash memory cells of claim 9 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 18

Dependent Claim 24 words

The array of flash memory cells of claim 15 , wherein the plurality of control gate lines are disposed vertically above the floating gates.

Claim 19

Dependent Claim 74 words

The array of flash memory cells of claim 9 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 20

Dependent Claim 37 words

The array of flash memory cells of claim 9 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 21

Dependent Claim 47 words

The array of flash memory cells of claim 9 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control gate lines.

Claim 22

Dependent Claim 75 words

The array of flash memory cells of claim 9 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 23

Dependent Claim 193 words

A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a vertical non-volatile memory cell including: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate.

Claim 24

Dependent Claim 193 words

A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a vertical non-volatile memory cell including: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate.

Claim 25

Dependent Claim 219 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein at least one of the memory device and processor includes an array of depletion mode flash memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash memory cells.

Claim 26

Dependent Claim 219 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein at least one of the memory device and processor includes an array of depletion mode flash memory cells, comprising: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gates are separated from the floating gates by a low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash memory cells.

Claim 27

Dependent Claim 64 words

The electronic system of claim 22 , wherein the asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 28

Dependent Claim 31 words

The electronic system of claim 22 , wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Claim 29

Dependent Claim 60 words

The electronic system of claim 22 , wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate.

Claim 30

Dependent Claim 55 words

The flash memory array of claim 25 , wherein the metal layer formed on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

Claim 31

Dependent Claim 50 words

The electronic system of claim 22 , wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 32

Dependent Claim 65 words

The electronic system of claim 22 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 33

Dependent Claim 71 words

The electronic system of claim 22 , wherein the plurality of control gate lines are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 34

Dependent Claim 34 words

The electronic system of claim 22 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 35

Dependent Claim 43 words

The electronic system of claim 22 , wherein the plurality of control gate lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 36

Dependent Claim 72 words

The electronic system of claim 22 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 37

Dependent Claim 21 words

The electronic system of claim 22 , wherein the plurality of control gate lines are disposed vertically above the floating gates.

Claim 38

Independent Claim 117 words

A method of forming a floating gate transistor, comprising: forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; and forming an asymmetrical low tunnel barrier intergate insulator to separate the control gate from the floating gate, wherein forming the low tunnel barrier intergate insulator includes a forming low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate.

Claim 39

Independent Claim 117 words

A method of forming a floating gate transistor, comprising: forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; and forming an asymmetrical low tunnel barrier intergate insulator to separate the control gate from the floating gate, wherein forming the low tunnel barrier intergate insulator includes a forming low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate.

Claim 40

Dependent Claim 65 words

The method of claim 34 , wherein forming the asymmetrical low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , Zro 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 41

Dependent Claim 33 words

The method of claim 34 , wherein forming the floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the asymmetrical low tunnel barrier intergate insulator.

Claim 42

Dependent Claim 61 words

The method of claim 36 , wherein forming the control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate.

Claim 43

Dependent Claim 53 words

The method of claim 37 , wherein forming the metal layer on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

Claim 44

Independent Claim 221 words

A method for forming an array of flash memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gate lines are separated from the floating gates by an asymmetrical low tunnel barrier intergate insulator, wherein forming the asymmetrical low tunnel barrier intergate insulator includes a forming low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash memory cells.

Claim 45

Independent Claim 221 words

A method for forming an array of flash memory cells, comprising: forming a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; forming a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; forming a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gate lines are separated from the floating gates by an asymmetrical low tunnel barrier intergate insulator, wherein forming the asymmetrical low tunnel barrier intergate insulator includes a forming low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and forming a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash memory cells.

Claim 46

Dependent Claim 65 words

The method of claim 39 , wherein forming the asymmetrical low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 47

Dependent Claim 32 words

The method of claim 39 , wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Claim 48

Dependent Claim 61 words

The method of claim 41 , wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator, wherein the metal layer formed on the polysilicon control gate includes a metal layer that has a different work function than the metal layer formed on the floating gate.

Claim 49

Dependent Claim 53 words

The method of claim 42 , wherein forming the metal layer on the floating gate includes a parent metal for the asymmetrical low tunnel barrier intergate insulator and the metal layer formed on the control gate includes a metal layer having a work function in the range of 2.7 eV to 5.8 eV.

Claim 50

Dependent Claim 50 words

The method of claim 39 , wherein forming each floating gate includes forming a vertical floating gate in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

Claim 51

Dependent Claim 69 words

The method of claim 39 , wherein forming the plurality of control gate lines includes forming each control gate line in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 52

Dependent Claim 70 words

The method of claim 39 , wherein forming the plurality of control gate lines includes forming a pair of control gate lines in each trench below the top surface of the pillar and between the pair of floating gates such that each control gate line addresses a floating gate on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

Claim 53

Dependent Claim 46 words

The method of claim 39 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates such that each pair of floating gates shares a single control gate line.

Claim 54

Dependent Claim 62 words

The method of claim 39 , wherein forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates, and forming the plurality of control lines such that each one of the pair of floating gates is addressed by an independent one of the plurality of control lines.

Claim 55

Dependent Claim 72 words

The method of claim 39 , wherein forming each floating gate includes forming a horizontally oriented floating gate in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposite sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

Claim 56

Dependent Claim 34 words

The method of claim 49 , wherein the forming the plurality of control gate lines includes forming the control gate lines such that the control gate lines are disposed vertically above the floating gates.

Claim 57

Independent Claim 146 words

A method for operating a non-volatile memory cell, comprising: writing to a floating gate of the non-volatile memory cell using channel hot electron injection, wherein the non-volatile memory cell includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate through the asymmetrical low tunnel barrier insulator.

Claim 58

Independent Claim 146 words

A method for operating a non-volatile memory cell, comprising: writing to a floating gate of the non-volatile memory cell using channel hot electron injection, wherein the non-volatile memory cell includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate through the asymmetrical low tunnel barrier insulator.

Claim 59

Dependent Claim 51 words

The method of claim 51 , wherein erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate through the asymmetrical low tunnel barrier insulator includes: providing a negative voltage to the substrate; and providing a large positive voltage to the control gate.

Claim 60

Dependent Claim 34 words

The method of claim 51 , wherein the method further includes writing to the floating gate by tunneling electrons from the control gate to the floating gate through the asymmetrical low tunnel barrier insulator.

Claim 61

Dependent Claim 49 words

The method of claim 53 , wherein writing to the floating gate by tunneling electrons from the control gate to the floating gate through the asymmetrical low tunnel barrier insulator further includes: applying a positive voltage to the substrate; and applying a large negative voltage to the control gate.

Claim 62

Dependent Claim 86 words

The method of claim 51 , wherein tunneling electrons from the floating gate to the control gate through the asymmetrical low tunnel barrier insulator includes tunneling electrons from the floating gate to the control gate through an asymmetrical low tunnel barrier insulator selected from the group consisting of Al 2 O 3 , Ta 2 O 5 , TiO 2 , ZrO 2 , Nb 2 O 5 , SrBi 2 Ta 2 O 3 , SrTiO 3 , PbTiO 3 , and PbZrO 3 .

Claim 63

Dependent Claim 42 words

The method of claim 51 , wherein tunneling electrons from the floating gate to the control gate through the asymmetrical low tunnel barrier insulator includes tunneling electrons through the asymmetrical low tunnel barrier insulator having a barrier energy of approximately 2.0 eV.

Claim 64

Dependent Claim 65 words

The method of claim 51 , wherein tunneling electrons from the floating gate to the control gate through the asymmetrical low tunnel barrier insulator includes tunneling electrons from a metal layer formed on the floating gate in contact with the low tunnel barrier intergate insulator to a metal layer formed on the control gate and also in contact with the low tunnel barrier intergate insulator.

Claim 65

Independent Claim 265 words

A method for operating an array of flash memory cells, comprising: writing to one or more floating gates for a number of non-volatile memory cells in the array of flash memory cells using channel hot electron injection, the array of flash memory cells includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gate lines are separated from the floating gates by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells; and erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates through the asymmetrical low tunnel barrier insulator.

Claim 66

Independent Claim 265 words

A method for operating an array of flash memory cells, comprising: writing to one or more floating gates for a number of non-volatile memory cells in the array of flash memory cells using channel hot electron injection, the array of flash memory cells includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of flash memory cells, wherein the number of control gate lines are separated from the floating gates by an asymmetrical low tunnel barrier intergate insulator having a number of small compositional ranges such that gradients can be formed by an applied electric field which produce different barrier heights at an interface with the floating gate and control gate; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of flash cells; and erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates through the asymmetrical low tunnel barrier insulator.

Claim 67

Dependent Claim 72 words

The method of claim 58 , wherein erasing charge from the one or more floating gates by tunneling electrons off of the floating gate and onto the number of control gates through the asymmetrical low tunnel barrier insulator further includes: providing a negative voltage to a substrate of one or more non-volatile memory cells; and providing a large positive voltage to the control gate for the one or more non-volatile memory cells.

Claim 68

Dependent Claim 57 words

The method of claim 59 , wherein the method further includes erasing an entire row of non-volatile memory cells by providing a negative voltage to all of the substrates along an entire row of non-volatile memory cells and providing a large positive voltage to all of the control gates along the entire row of non-volatile memory cells.

Claim 69

Dependent Claim 56 words

The method of claim 59 , wherein the method further includes erasing an entire block of non-volatile memory cells by providing a negative voltage to all of the substrates along multiple rows of non-volatile memory cells and providing a large positive voltage to all of the control gates along the multiple rows of non-volatile memory cells.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2008-10-03	2009-04-04	2009-10-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2012-10-03	2013-04-04	2013-10-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2016-10-03	2017-04-04	2017-10-04	$7700.00	Window Closed / Lapsed

Programmable array logic or memory devices with asymmetrical tunnel barriers

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