US6732307B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for storing trace information
Assignee: Renesas Electronics Corp
•
Filing: 1999-10-01
•
Granted: 2004-05-04
•
Expires: 2019-10-01
Abstract
Abstract A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
Inventors
- 👤 David Alan Edwards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/3648
Claims Analysis
Total Claims: 72
Claim 1
Independent Claim
110 words
An integrated circuit comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor in at least one of the following modes: a mode wherein the FIFO buffer is configured as a circular buffer in the debug module to overwrite old messages in the FIFO by new messages; a mode wherein the debug module stops storing trace information when the FIFO buffer is full; and a mode wherein the debug module discards additional trace information when the FIFO buffer is full.
Claim 2
Dependent Claim
110 words
An integrated circuit comprising: at least one processor; a debug module operatively connected to the processor, the debug module including a first-in first out (FIFO) buffer wherein the debug module is configurable by a user to store trace information produced by the processor in at least one of the following modes: a mode wherein the FIFO buffer is configured as a circular buffer in the debug module to overwrite old messages in the FIFO by new messages; a mode wherein the debug module stops storing trace information when the FIFO buffer is full; and a mode wherein the debug module discards additional trace information when the FIFO buffer is full.
Claim 3
Dependent Claim
26 words
The integrated circuit according to claim 1 , wherein the debug module provides an indication to the processor that the FIFO is approaching a full level.
Claim 4
Dependent Claim
29 words
The integrated circuit according to claim 2 , wherein the debug module provides the indication within a finite number of storage locations from the full level of the FIFO.
Claim 5
Dependent Claim
56 words
The integrated circuit according to claim 1 , wherein the FIFO includes a pointer to where indicating a write location for an first entry and a pointer for reading an second entry, wherein the first entry is a first entry in the FIFO buffer and the second entry is a last entry in the FIFO buffer.
Claim 6
Dependent Claim
37 words
The integrated circuit according to claim 1 , in the mode wherein the debug module stops storing trace information when the FIFO buffer is full, the integrated circuit generates an interrupt to disable storing of trace information.
Claim 7
Dependent Claim
26 words
The integrated circuit according to claim 5 , wherein the integrated circuit executes handler code that accepts the interrupt and disables the storing of trace information.
Claim 8
Dependent Claim
23 words
The integrated circuit according to claim 6 , wherein the debug module communicates with a tool to empty entries in the FIFO buffer.
Claim 9
Dependent Claim
17 words
The integrated circuit according to claim 7 , wherein the tool is capable of enabling trace mode.
Claim 10
Dependent Claim
21 words
The integrated circuit according to claim 7 , wherein the processor is disabled as entries are emptied from the FIFO buffer.
Claim 11
Dependent Claim
34 words
The integrated circuit according to claim 5 , wherein the integrated circuit is configured to stall the processor and provides an indication to an external system, the indication indicating that the processor is stalled.
Claim 12
Dependent Claim
17 words
The integrated circuit according to claim 1 , wherein the trace information includes address and message information.
Claim 13
Dependent Claim
17 words
The integrated circuit according to claim 1 , wherein the trace information is stored on byte-based boundaries.
Claim 14
Dependent Claim
20 words
The integrated circuit according to claim 1 , wherein the trace information stored in the FIFO includes variable length messages.
Claim 15
Dependent Claim
22 words
The integrated circuit according to claim 1 , wherein the trace information is stored as trace entries each located on byte based-boundaries.
Claim 16
Dependent Claim
15 words
The integrated circuit according to claim 14 , wherein the entries are compressed trace messages.
Claim 17
Dependent Claim
19 words
The integrated circuit according to claim 15 , wherein the compressed trace messages include compressed timing and address information.
Claim 18
Dependent Claim
25 words
The integrated circuit according to claim 1 , wherein the trace information includes a plurality of state information bits representing triggered conditions of the processor.
Claim 19
Dependent Claim
19 words
The integrated circuit according to claim 1 , wherein storage locations of the FIFO are memory mapped storage registers.
Claim 20
Dependent Claim
16 words
The integrated circuit according to claim 18 , wherein the storage registers are control FIFO registers.
Claim 21
Dependent Claim
17 words
The integrated circuit according to claim 18 , wherein the storage registers are display state FIFO registers.
Claim 22
Dependent Claim
23 words
The integrated circuit according to claim 18 , wherein the FIFO receives trace information from a capture buffer operatively coupled to the processor.
Claim 23
Dependent Claim
33 words
The integrated circuit according to claim 21 , the circuit further comprising a system bus, wherein the capture buffer is operatively coupled to the processor by a bus separate from the system bus.
Claim 24
Dependent Claim
25 words
The integrated circuit according to claim 18 , wherein trace information is extracted out of the FIFO into at least one memory mapped storage register.
Claim 25
Dependent Claim
23 words
The integrated circuit according to claim 23 , wherein trace information is extracted out of the FIFO one trace message at a time.
Claim 26
Dependent Claim
17 words
The integrated circuit according to claim 1 , wherein the FIFO is accessed without perturbing external memory.
Claim 27
Dependent Claim
22 words
The integrated circuit according to claim 1 , wherein trace information is stored in the FIFO buffer and an external memory device.
Claim 28
Dependent Claim
20 words
The integrated circuit according to claim 1 , wherein trace entries are stored in the FIFO buffer at constant intervals.
Claim 29
Dependent Claim
17 words
The integrated circuit according to claim 27 , wherein the constant intervals are sixty four bit intervals.
Claim 30
Dependent Claim
25 words
The integrated circuit according to claim 1 , wherein the debug module provides a control signal to the processor to stall execution of new instructions.
Claim 31
Dependent Claim
46 words
The integrated circuit according to claim 29 , wherein the debug module provides the control signal to stall the processor in response to the FIFO buffer reaching a level of storage within a finite number of storage locations from the full level of the FIFO buffer.
Claim 32
Dependent Claim
36 words
The integrated circuit according to claim 30 , wherein the finite number of storage locations is greater than or equal to a number of trace messages that are capable of being produced by the stalled processor.
Claim 33
Dependent Claim
27 words
The integrated circuit according to claim 31 , wherein the processor is stalled within a finite number of processor cycles to prevent overflow of the FIFO buffer.
Claim 34
Dependent Claim
24 words
The integrated circuit according to claim 30 , wherein the debug module provides an external trigger signal to indicate that the processor is stalled.
Claim 35
Dependent Claim
21 words
The integrated circuit according to claim 1 , wherein trace entries are stored in the FIFO buffer at variable length boundaries.
Claim 36
Dependent Claim
18 words
The integrated circuit according to claim 1 , wherein trace information is generated based on a trace mode.
Claim 37
Dependent Claim
29 words
The integrated circuit according to claim 35 , wherein the trace mode is a mode wherein a trace message is generated for each of a plurality of processor states.
Claim 38
Dependent Claim
29 words
The integrated circuit according to claim 35 , wherein the trace mode is a mode wherein a single trace message is generated for a plurality of similar processor states.
Claim 39
Dependent Claim
35 words
The integrated circuit according to claim 37 , wherein a trace message is generated in response to a state change in which a processor state has become different from the plurality of similar processor states.
Claim 40
Dependent Claim
29 words
The integrated circuit according to claim 37 , wherein each of the plurality of similar processor states have a same instruction address range as the other similar processor states.
Claim 41
Dependent Claim
28 words
The integrated circuit according to claim 1 , wherein the circular buffer mode is a mode wherein an oldest trace entry is overwritten by a new trace message.
Claim 42
Dependent Claim
41 words
The integrated circuit according to claim 1 , wherein the debug module is configurable by a user in a mode wherein new trace messages exceeding a capability of the debug module are discarded in hardware without generating one or more interrupts.
Claim 43
Independent Claim
107 words
A method for processing trace information of an integrated circuit comprising at least one processor and a debug circuit, the method comprising: receiving trace information produced by the processor; and storing the trace information in the integrated circuit in at least one of the following modes: a mode wherein a buffer associated with the debug circuit is configured as a circular buffer in the debug circuit to overwrite old messages in the buffer by new messages; a mode wherein the debug circuit stops storing trace information when the buffer is full; and a mode wherein the debug circuit discards additional trace information when the buffer is full.
Claim 44
Independent Claim
107 words
A method for processing trace information of an integrated circuit comprising at least one processor and a debug circuit, the method comprising: receiving trace information produced by the processor; and storing the trace information in the integrated circuit in at least one of the following modes: a mode wherein a buffer associated with the debug circuit is configured as a circular buffer in the debug circuit to overwrite old messages in the buffer by new messages; a mode wherein the debug circuit stops storing trace information when the buffer is full; and a mode wherein the debug circuit discards additional trace information when the buffer is full.
Claim 45
Dependent Claim
25 words
The method according to claim 42 , the method further comprising providing an indication to the processor that the buffer is approaching a full level.
Claim 46
Dependent Claim
28 words
The method according to claim 43 , the method further comprising providing the indication within a finite number of storage locations from the full level of the buffer.
Claim 47
Dependent Claim
27 words
The method according to claim 44 , the method further comprising a step of providing a control signal to the processor to stall execution of new instructions.
Claim 48
Dependent Claim
45 words
The method according to claim 45 , wherein the step of providing a control signal to stall the processor is provided in response to the buffer reaching a level of storage within a finite number of storage locations from the full level of the buffer.
Claim 49
Dependent Claim
35 words
The method according to claim 46 , wherein the finite number of storage locations is greater than or equal to a number of trace messages that are capable of being produced by the stalled processor.
Claim 50
Dependent Claim
25 words
The method according to claim 46 , wherein the processor is stalled within a finite number of processor cycles to prevent overflow of the buffer.
Claim 51
Dependent Claim
23 words
The method according to claim 45 , wherein the debug circuit provides an external trigger signal to indicate that the processor is stalled.
Claim 52
Dependent Claim
22 words
The method according to claim 43 , wherein the trace information is stored as trace entries each located on byte based boundaries.
Claim 53
Dependent Claim
14 words
The method according to claim 50 , wherein the entries are compressed trace messages.
Claim 54
Dependent Claim
18 words
The method according to claim 51 , wherein the compressed trace messages include compressed timing and address information.
Claim 55
Dependent Claim
24 words
The method according to claim 43 , wherein the trace information includes a plurality of state information bits representing triggered conditions of the processor.
Claim 56
Dependent Claim
18 words
The method according to claim 43 , wherein storage locations of the buffer are memory mapped storage registers.
Claim 57
Dependent Claim
21 words
The method according to claim 43 , the method further comprising a step of accessing the buffer without perturbing external memory.
Claim 58
Dependent Claim
53 words
The method according to claim 42 , wherein the buffer includes a pointer to where indicating a write location for an first entry and a pointer for reading an second entry, wherein the first entry is a first entry in the buffer and the second entry is a last entry in the buffer.
Claim 59
Dependent Claim
39 words
The method according to claim 42 , wherein the mode wherein the debug circuit stops storing trace information when the buffer is full, the method further comprises a step of generating an interrupt to disable storing of trace information.
Claim 60
Dependent Claim
29 words
The method according to claim 57 , further comprising a step of executing handler code that performs steps of accepting the interrupt and disabling the storing of trace information.
Claim 61
Dependent Claim
24 words
The method according to claim 58 , the method further comprising a step of communicating with a tool to empty entries in the buffer.
Claim 62
Dependent Claim
16 words
The method according to claim 59 , wherein the tool is capable of enabling trace mode.
Claim 63
Dependent Claim
24 words
The method according to claim 59 , the method further comprising a step of disabling the processor as entries are emptied from the buffer.
Claim 64
Dependent Claim
32 words
The method according to claim 57 , the method further comprising steps of stalling the processor and providing an indication to an external system, the indication indicating that the processor is stalled.
Claim 65
Dependent Claim
16 words
The method according to claim 42 , wherein the trace information includes address and message information.
Claim 66
Dependent Claim
17 words
The method according to claim 42 , wherein the trace information is stored on byte based boundaries.
Claim 67
Dependent Claim
19 words
The method according to claim 42 , wherein the trace information stored in the buffer includes variable length messages.
Claim 68
Dependent Claim
22 words
The method according to claim 42 , the method further comprising a step of generating trace information based on a trace mode.
Claim 69
Dependent Claim
28 words
The method according to claim 66 , wherein the trace mode is a mode wherein a trace message is generated for each of a plurality of processor states.
Claim 70
Dependent Claim
28 words
The method according to claim 66 , wherein the trace mode is a mode wherein a single trace message is generated for a plurality of similar processor states.
Claim 71
Dependent Claim
34 words
The method according to claim 68 , wherein a trace message is generated in response to a state change in which a processor state has become different from the plurality of similar processor states.
Claim 72
Dependent Claim
28 words
The method according to claim 68 , wherein each of the plurality of similar processor states have a same instruction address range as the other similar processor states.
References Cited (Backward Citations)
EP0165600B1
Cited
US5440705A
Cited
US4814981A
Cited
US5251311A
Cited
US5386565A
Cited
US5452432A
Cited
US5355487A
Cited
US5682545A
Cited
US5423050A
Cited
US5724549A
Cited
US5479652B1
Cited
US5479652A
Cited
US5483518A
Cited
US5513317A
Cited
US5448576A
Cited
US5608881A
Cited
US5530965A
Cited
US5832248A
Cited
US5627842A
Cited
US5455936A
Cited
US5598551A
Cited
EP0636976B1
Cited
EP0636976A1
Cited
US5590354A
Cited
US5930523A
Cited
EP0652516A1
Cited
US5596734A
Cited
US5828825A
Cited
US5434804A
Cited
US5625785A
Cited
US5488688A
Cited
US5930833A
Cited
US5809293A
Cited
EP0702239A2
Cited
EP0702239A3
Cited
US5835963A
Cited
JPH08320796A
Cited
US5796978A
Cited
US5848247A
Cited
US5613153A
Cited
US5751621A
Cited
US5657273A
Cited
US5943498A
Cited
EP0720092A1
Cited
US5778237A
Cited
US5862387A
Cited
US5867726A
Cited
US5570375A
Cited
US5659679A
Cited
US5860127A
Cited
JPH08329687A
Cited
US5774701A
Cited
US5708773A
Cited
US5737516A
Cited
US6035422A
Cited
US5704034A
Cited
US5964893A
Cited
US5884092A
Cited
US5884023A
Cited
JPH09212358A
Cited
US5950012A
Cited
JPH09311786A
Cited
US5724505A
Cited
US5978874A
Cited
JPH10106269A
Cited
US6145099A
Cited
US5781558A
Cited
US5768152A
Cited
JPH10177520A
Cited
JPH10124484A
Cited
US5918045A
Cited
US5848264A
Cited
US5983379A
Cited
US5983017A
Cited
US5953538A
Cited
US5771240A
Cited
US5956477A
Cited
US5996092A
Cited
US5999112A
Cited
US5983366A
Cited
US5896550A
Cited
US6094729A
Cited
US6148381A
Cited
US6189140B1
Cited
US6185732B1
Cited
US6167536A
Cited
US6154857A
Cited
US6314530B1
Cited
US5978902A
Cited
US6142683A
Cited
US5944841A
Cited
US6167499A
Cited
US6282701B1
Cited
US5938778A
Cited
US6175914B1
Cited
EP0933926A1
Cited
US6108761A
Cited
EP0945805A1
Cited
EP0959411A1
Cited
US6145123A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-05-04 | 2007-11-03 | 2008-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-05-04 | 2011-11-03 | 2012-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-05-04 | 2015-11-03 | 2016-05-04 | $7700.00 | Window Closed / Lapsed |