US5944841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor with built-in instruction tracing capability
Assignee: Advanced Micro Devices Inc
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Filing: 1997-04-15
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Granted: 1999-08-31
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Expires: 2017-04-15
Abstract
Abstract A computer system employing an instruction tracing mechanism includes a memory and a CPU. The memory includes a trace buffer used to store records of the instruction tracing. Entries in the trace buffer are pointed to by a tracer pointer. The memory is coupled to the CPU via a bus interface unit. Instructions are passed from the memory to the CPU via the bus interface unit and are queued in an instruction cache, which includes a byte queue. The CPU further includes a control unit coupled to a control register, the tracer pointer and a maskable ROM. The control unit controls and activates the instruction tracing mechanism. In response to software sitting a bit in the control register, the control unit functions to retrieve a special tracing microcode sequence from MROM to provide a trace record of the instructions as they are passed to the instruction decoders. A counting mechanism may also be activated to count instructions and store the count in the memory. The computer system further includes a register file coupled to the instruction decoders and functional units, also coupled to instruction decoders, to receive and process the instructions.
Inventors
- 👤 David S. Christie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
128 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record.
Claim 2
Dependent Claim
128 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record.
Claim 3
Dependent Claim
35 words
The microprocessor of claim 1, further including an MROM unit coupled to said instruction trace control unit and configured to provide an instruction tracing routine responsive to a command from said instruction trace control unit.
Claim 4
Dependent Claim
25 words
The microprocessor of claim 2, wherein said instruction trace control unit provides said command responsive to the setting of a bit in a control register.
Claim 5
Dependent Claim
50 words
The microprocessor of claim 1, wherein said instruction trace control unit is further coupled to a tracer pointer register, wherein said tracer pointer register is configured to provide a pointer to a location in memory wherein said trace record of said each one of said plurality of instructions is stored.
Claim 6
Dependent Claim
85 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction counter control unit coupled between said instruction cache and said at least one decoder, said instruction counter control unit configured to control a counting mechanism, said counting mechanism configured to count a number of occurrences of each instruction defined in an instruction set executable by said microprocessor.
Claim 7
Dependent Claim
85 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction counter control unit coupled between said instruction cache and said at least one decoder, said instruction counter control unit configured to control a counting mechanism, said counting mechanism configured to count a number of occurrences of each instruction defined in an instruction set executable by said microprocessor.
Claim 8
Dependent Claim
35 words
The microprocessor of claim 5, further including an MROM unit coupled to said instruction counter control unit and configured to provide an instruction counting routine responsive to a command from said instruction counter control unit.
Claim 9
Dependent Claim
25 words
The microprocessor of claim 6, wherein said instruction counter control unit provides said command responsive to the setting of a bit in a control register.
Claim 10
Dependent Claim
45 words
The microprocessor of claim 5, wherein said instruction counter control unit is further coupled to a tracer register, wherein said tracer register is configured to provide a base address of a region of memory configured to store counters generated by said instruction counter control unit.
Claim 11
Dependent Claim
146 words
A computer system, comprising: a processor including: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from an instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record; and a memory unit having a predetermined region configured to store said trace record.
Claim 12
Dependent Claim
146 words
A computer system, comprising: a processor including: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from an instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record; and a memory unit having a predetermined region configured to store said trace record.
Claim 13
Dependent Claim
47 words
The computer system of claim 9, wherein said processor includes a tracer pointer register configured to point to a location in said predetermined region of said memory corresponding to where said trace record corresponding to a particular one of said plurality of instructions is to be stored.
Claim 14
Dependent Claim
49 words
The computer system of claim 10 further comprising a storage device external to said memory, wherein said processor is configured to monitor whether said predetermined region of said memory is full, and activate a routine to save contents of said predetermined region of said memory to said storage device.
Claim 15
Dependent Claim
17 words
The computer system of claim 11, wherein said routine is activated by generating a system management interrupt.
Claim 16
Dependent Claim
34 words
The computer system of claim 11, wherein said monitor compares a value of said tracer pointer to a predetermined value, and activates said routine if said tracer pointer is equal to said predetermined value.
Claim 17
Dependent Claim
39 words
The computer system as recited in claim 12, wherein said instruction trace control unit is configured to resume providing said trace records after said routine saves said contents of said predetermined region of said memory to said storage device.
Claim 18
Dependent Claim
170 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record, and wherein said trace record further comprises one or more additional trace records, each of said basic trace record and said one or more additional trace records including a trace type which identifies said basic trace record and said additional trace records.
Claim 19
Dependent Claim
170 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record, and wherein said trace record further comprises one or more additional trace records, each of said basic trace record and said one or more additional trace records including a trace type which identifies said basic trace record and said additional trace records.
Claim 20
Dependent Claim
17 words
The microprocessor as recited in claim 15 wherein said additional trace records comprise a taken branch record.
Claim 21
Dependent Claim
26 words
The microprocessor as recited in claim 15 wherein said additional trace records comprise a repeated string instruction information record and a repeated string early termination record.
Claim 22
Dependent Claim
16 words
The microprocessor as recited in claim 15 wherein said additional trace records comprise an exception/interrupt record.
Claim 23
Dependent Claim
17 words
The microprocessor as recited in claim 15 wherein said additional trace records comprise a task switch records.
Claim 24
Dependent Claim
19 words
The microprocessor as recited in claim 15 wherein said additional trace records comprise a special record for string/CR3 conditions.
Claim 25
Dependent Claim
209 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction counter control unit coupled between said instruction cache and said at least one decoder, said instruction counter control unit configured to control a counting mechanism, said counting mechanism configured to count a number of occurrences of each instruction defined in an instruction set executable by said microprocessor, and wherein said instruction counter control unit is further coupled to a tracer register, wherein said tracer register is configured to provide a base address of a region of memory configured to store counters generated by said instruction counter control unit, and wherein said microprocessor is configured to form an index into said region of memory to select one of said counters corresponding to one of said plurality of instructions, said index comprising: (i) one or more bits indicative of a mode in which said microprocessor is operating, (ii) one or more bits indicative of a mode of an instruction, (iii) an opcode of said one of said plurality of instructions, and (iv) an addressing mode of said one of said plurality of instructions.
Claim 26
Dependent Claim
209 words
A microprocessor comprising: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from said instruction cache; and an instruction counter control unit coupled between said instruction cache and said at least one decoder, said instruction counter control unit configured to control a counting mechanism, said counting mechanism configured to count a number of occurrences of each instruction defined in an instruction set executable by said microprocessor, and wherein said instruction counter control unit is further coupled to a tracer register, wherein said tracer register is configured to provide a base address of a region of memory configured to store counters generated by said instruction counter control unit, and wherein said microprocessor is configured to form an index into said region of memory to select one of said counters corresponding to one of said plurality of instructions, said index comprising: (i) one or more bits indicative of a mode in which said microprocessor is operating, (ii) one or more bits indicative of a mode of an instruction, (iii) an opcode of said one of said plurality of instructions, and (iv) an addressing mode of said one of said plurality of instructions.
Claim 27
Dependent Claim
188 words
A computer system, comprising: a processor including: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from an instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record, and wherein said trace record further comprises one or more additional trace records, each of said basic trace record and said one or more additional trace records including a trace type which identifies said basic trace record and said additional trace records; and a memory unit having a predetermined region configured to store said trace record.
Claim 28
Dependent Claim
188 words
A computer system, comprising: a processor including: an instruction cache configured to store a plurality of instructions forming an instruction stream; at least one decoder configured to decode said plurality of instructions upon fetch thereof from an instruction cache; and an instruction trace control unit coupled between said instruction cache and said at least one decoder, said instruction trace control unit configured to provide a trace record of each one of said plurality of instructions, wherein said trace record of said each one of said plurality of instructions comprises a basic trace record, and wherein said basic trace record includes information identifying at least one of: (i) an operand addressing mode and (ii) a memory addressing mode employed by said one of said plurality of instructions corresponding to said basic trace record, and wherein said trace record further comprises one or more additional trace records, each of said basic trace record and said one or more additional trace records including a trace type which identifies said basic trace record and said additional trace records; and a memory unit having a predetermined region configured to store said trace record.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |