US4349873A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor interrupt processing
Assignee: Motorola Solutions Inc
•
Filing: 1980-04-02
•
Granted: 1982-09-14
•
Expires: 2000-04-02
Abstract
Abstract An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated. Error circuitry is provided to detect spurious interrupts.
Inventors
- 👤 Thomas G. Gunter
- 👤 John E. Zolnowsky
- 👤 Lester M. Crudele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0745; G06F11/0751; G06F11/0754; G06F11/0757
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
362 words
In a data processor for executing operations upon digital information in response to a plurality of instruction programs, an interrupt circuit comprising: first means adapted for coupling to first and second types of circuitry external to the data processor, for receiving interrupt signals from both the first and second types of external circuitry representing requests to interrupt the execution of an instruction program currently being executed by the data processor in order to execute another of the plurality of instruction programs; second means adapted for coupling to the first type of the external circuitry, for receiving from the first type of external circuitry a vector number indicative of a vector address within a predetermined portion of the address space of the data processor which contains an address vector comprising an address within one of the plurality of instruction programs; third means coupled to the first means and having an output adapted for coupling to the first and second types of external circuitry, for providing, in response to the interrupt signal, a granting signal to the first and second types of external circuitry indicating that the interrupt request has been granted by the data processor; fourth means having an input adapted for coupling to the first type of external circuitry, for receiving a first acknowledgement signal provided by the first type of external circuitry indicating that a vector number has been provided to the second means, and for latching, in response to the first acknowledgement signal, the vector number received by the second means; fifth means having an input adapted for coupling to the second type of external circuitry, for receiving a second acknowledgement signal provided by the second type of external circuitry indicating that a vector number has not been provided to the second means, and for providing, in response to the second acknowledgement signal, a predetermined vector number independent of any vector number received by the second means; and sixth means coupled to the fourth and fifth means, for generating the vector address indicated by the vector number provided by the fifth means is so provided and the vector address indicated by the vector number latched by the fourth means otherwise.
Claim 2
Dependent Claim
362 words
In a data processor for executing operations upon digital information in response to a plurality of instruction programs, an interrupt circuit comprising: first means adapted for coupling to first and second types of circuitry external to the data processor, for receiving interrupt signals from both the first and second types of external circuitry representing requests to interrupt the execution of an instruction program currently being executed by the data processor in order to execute another of the plurality of instruction programs; second means adapted for coupling to the first type of the external circuitry, for receiving from the first type of external circuitry a vector number indicative of a vector address within a predetermined portion of the address space of the data processor which contains an address vector comprising an address within one of the plurality of instruction programs; third means coupled to the first means and having an output adapted for coupling to the first and second types of external circuitry, for providing, in response to the interrupt signal, a granting signal to the first and second types of external circuitry indicating that the interrupt request has been granted by the data processor; fourth means having an input adapted for coupling to the first type of external circuitry, for receiving a first acknowledgement signal provided by the first type of external circuitry indicating that a vector number has been provided to the second means, and for latching, in response to the first acknowledgement signal, the vector number received by the second means; fifth means having an input adapted for coupling to the second type of external circuitry, for receiving a second acknowledgement signal provided by the second type of external circuitry indicating that a vector number has not been provided to the second means, and for providing, in response to the second acknowledgement signal, a predetermined vector number independent of any vector number received by the second means; and sixth means coupled to the fourth and fifth means, for generating the vector address indicated by the vector number provided by the fifth means is so provided and the vector address indicated by the vector number latched by the fourth means otherwise.
Claim 3
Dependent Claim
58 words
A data processor according to claim 1 wherein the interrupt signals received by the first means are representative of a priority level associated with the external circuitry which requested an interrupt, and the vector number provided by the fifth means is in a predetermined relationship to the priority level associated with the external circuitry which requested the interrupt.
Claim 4
Dependent Claim
59 words
A data processor according to claim 2 further comprising: seventh means coupled to the first means and adapted for coupling to the first and second types of external circuitry, for providing to the first and second types of external circuitry a priority level associated with the external circuitry for which the granting signal is generated by the third means.
Claim 5
Dependent Claim
126 words
The data processor of claim 2 wherein the data processor further comprises a register for storing a priority level associated with the instruction program currently being executed thereby, and wherein the interrupt circuit further comprises seventh means coupled to the sixth means and to the register, for interrupting the execution by the data processor of the instruction program currently being executed thereby when the priority level of such instruction program is lower than the priority level associated with the external circuitry for which the granting signal has been generated by the third means, and thereafter forcing the data processor to begin execution of the one of the plurality of instruction programs whose address comprises the address vector in the vector address generated by the sixth means.
References Cited (Backward Citations)
US3789365A
Cited
US4005391A
Cited
US4001783A
Cited
US3993981A
Cited
US4020471A
Cited
US4023143A
Cited
US4034349A
Cited
US4056847A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-09-13 | 1986-03-15 | 1986-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-09-13 | 1990-03-15 | 1990-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-09-13 | 1994-03-15 | 1994-09-14 | $7700.00 | Window Closed / Lapsed |