Fixed priority interrupt control circuit

Claim 1

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to the interrupt signals, the apparatus comprising: a. means for storing each of the interrupt signals, said means including means for clearing an interrupt signal in response to the processing unit accepting said interrupt signal; b. means responsive to the storing means for generating a coded interrupt signal representing the highest priority interrupt signal contained in the storing means; c. a last-in first-out memory having an input connected to the generating means and having an output connected to the processing unit for transferring the highest priority coded interrupt signal in the memory to the processing unit; and d. means responsive to the generating means and the processing unit and connected to the memory for controlling the transfer of the coded interrupt signal to the memory in response to the coded interrupt signal having a priority equal to or higher than the highest priority coded interrupt signal currently in the memory, whereby the coded interrupt signal is transferred to the processing unit, said controlling means including means for shifting the next highest priority signal in the memory to the memory output in response to said processing unit executing the operation defined by the coded interrupt signal.

Claim 2

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to the interrupt signals, the apparatus comprising: a. means for storing each of the interrupt signals, said means including means for clearing an interrupt signal in response to the processing unit accepting said interrupt signal; b. means responsive to the storing means for generating a coded interrupt signal representing the highest priority interrupt signal contained in the storing means; c. a last-in first-out memory having an input connected to the generating means and having an output connected to the processing unit for transferring the highest priority coded interrupt signal in the memory to the processing unit; and d. means responsive to the generating means and the processing unit and connected to the memory for controlling the transfer of the coded interrupt signal to the memory in response to the coded interrupt signal having a priority equal to or higher than the highest priority coded interrupt signal currently in the memory, whereby the coded interrupt signal is transferred to the processing unit, said controlling means including means for shifting the next highest priority signal in the memory to the memory output in response to said processing unit executing the operation defined by the coded interrupt signal.

Claim 8

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to the interrupt signals, said processing unit producing an acknowledge signal in response to a request signal generated by said apparatus and a reset signal in response to the execution of the interrupt requested, the apparatus comprising: a. means for storing each of the interrupt signals in a single storage element, said storing means including means for clearing a stored interrupt signal in response to an acknowledge signal produced in response to said stored interrupt signal; b. means responsive to the storing means for generating a coded signal representing the highest priority interrupt signal contained in the storing means; c. a last-in first-out memory responsive to the coded signal and producing an output signal to the processing unit representing the highest priority coded signal stored in the memory; d. means connected to the processing unit and responsive to the coded signal and the output signal for producing the request signal in response to the coded signal having a priority at least as high as the priority of the output signal; and e. means responsive to the processing unit and connected to the memory for causing in response to the acknowledge signal the coded signal to be transferred to the memory and become the output signal therefrom, said causing means further includes means for causing in response to the reset signal the next highest priority coded signal stored in the memory to become the output signal therefrom.

Claim 9

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to the interrupt signals, said processing unit producing an acknowledge signal in response to a request signal generated by said apparatus and a reset signal in response to the execution of the interrupt requested, the apparatus comprising: a. means for storing each of the interrupt signals in a single storage element, said storing means including means for clearing a stored interrupt signal in response to an acknowledge signal produced in response to said stored interrupt signal; b. means responsive to the storing means for generating a coded signal representing the highest priority interrupt signal contained in the storing means; c. a last-in first-out memory responsive to the coded signal and producing an output signal to the processing unit representing the highest priority coded signal stored in the memory; d. means connected to the processing unit and responsive to the coded signal and the output signal for producing the request signal in response to the coded signal having a priority at least as high as the priority of the output signal; and e. means responsive to the processing unit and connected to the memory for causing in response to the acknowledge signal the coded signal to be transferred to the memory and become the output signal therefrom, said causing means further includes means for causing in response to the reset signal the next highest priority coded signal stored in the memory to become the output signal therefrom.

Claim 10

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to said interrupt signals, said processing unit producing an acknowledge signal in response to a request signal generated by said apparatus and a reset signal in response to the execution of the requested interrupt, the apparatus comprising: a. a number of storage elements corresponding to the number of interrupt signals for producing a stored signal in response to the occurrence of an interrupt signal; b. an encoder element connected to the storage elements for generating a coded signal in response to a stored signal corresponding to the highest priority interrupt signal; c. a last-in first-out memory connected between the encoder element and the processing unit for storing the coded signals in order of descending priority and producing an output signal representing the highest priority coded signal stored, said memory having a first input to increment the output signal to a higher priority storage location and a second input to decrement the output signal to a lower priority storage location; d. a comparator circuit responsive to the encoder element and the memory and connected to the processing unit for producing the request signal in response to the coded signal having a priority equal to or higher than the output signal; e. means responsive to the processing unit and connected to the first and second inputs of the memory for 1. incrementing the memory and transferring the coded signal to the higher priority storage location in response to the acknowledge signal, and 2. decrementing the memory to the lower priority storage location in response to the reset signal; and f. means responsive to the processing unit and connected to the storage elements for resetting in response to the acknowledge signal the storage element containing the interrupt signal corresponding to the coded signal transferred to the memory.

Claim 11

An apparatus for controlling the transfer of interrupt signals to a processing unit according to predetermined levels of priority assigned to said interrupt signals, said processing unit producing an acknowledge signal in response to a request signal generated by said apparatus and a reset signal in response to the execution of the requested interrupt, the apparatus comprising: a. a number of storage elements corresponding to the number of interrupt signals for producing a stored signal in response to the occurrence of an interrupt signal; b. an encoder element connected to the storage elements for generating a coded signal in response to a stored signal corresponding to the highest priority interrupt signal; c. a last-in first-out memory connected between the encoder element and the processing unit for storing the coded signals in order of descending priority and producing an output signal representing the highest priority coded signal stored, said memory having a first input to increment the output signal to a higher priority storage location and a second input to decrement the output signal to a lower priority storage location; d. a comparator circuit responsive to the encoder element and the memory and connected to the processing unit for producing the request signal in response to the coded signal having a priority equal to or higher than the output signal; e. means responsive to the processing unit and connected to the first and second inputs of the memory for 1. incrementing the memory and transferring the coded signal to the higher priority storage location in response to the acknowledge signal, and 2. decrementing the memory to the lower priority storage location in response to the reset signal; and f. means responsive to the processing unit and connected to the storage elements for resetting in response to the acknowledge signal the storage element containing the interrupt signal corresponding to the coded signal transferred to the memory.