Priority vector interrupt system

Claim 1

In a data processing system capable of handling priority vectored interrupts, said system including means for generating address signals, including address bus means for conducting said address signals, data bus means for conducting data signals, timing signal means for supplying periodic signals, read signal means for supplying signals indicative of system read operations, write signal means for supplying signals representative of system write operations, a plurality of interrupt request signal means for supplying interrupt request signals representative of particular interrupts, each interrupt request signal having an assigned priority, decoder means responsive to said address signals when representative of a particular location for producing a control signal, storage means responsive to said timing signal means for storing the state of each of said plurality of interrupt request signals, priority encoder means responsive to the storage means for producing encoded signals representative of the active interrupt request signal having the highest assigned priority, first gating means responsive to said control signal and said read signal means for coupling said encoded signals to said data bus, the improvement comprising: second gating means responsive to said control signal and said write signal means for producing a latch signal; latching means for latching data bus signals in response to said latch signal; a plurality of third gating means, each responsive to a different one of the latched data bus signals and a different one of said plurality of interrupt request signals, for selectively coupling said interrupt request signals to said storage means.