Priority interruption circuits for digital computer systems

Claim 2

A peripheral unit for use in a digital computer system including a central processor unit and an input/output bus with a plurality of wires connected thereto, said peripheral unit connected to the input/output bus for receiving and transmitting control and data signals from and onto the bus wires, certain of the received control signals including selected channel signals identifying a priority level and a request synchronizing signal and following input granting signal, said peripheral unit comprising: A. means for transmitting a priority interruption signal onto the bus indicating a priority level, B. a comparator connected to said transmitting means and adapted to receive the selected channel signals for producing an output signal whenever said peripheral unit has requested a priority interruption at the level the selected channel signals identify. C. an input granting signal receiver for normally coupling the input granting signal through saId peripheral unit, said receiver being disabled in response to the combination of a signal from said comparator and a request synchronizing signal to thereby block the passage of the input granting signal through said peripheral unit, and D. means for transferring a digital interruption data word onto preselected bus wires when said receiver is disabled.

Claim 3

A peripheral unit as recited in claim 1 wherein the bus contains a plurality of priority interruption wires and said priority interruption signal transmitting means comprises: i. a priority register for storing a priority number in response to another control signal and selected data signals on the bus, ii. a gated decoder responsive to an input gating signal for converting the contents of said priority register into a signal on a corresponding priority interruption wire, and iii. means for producing the input gating signal.

Claim 4

A peripheral unit as recited in claim 1 wherein said digital interruption data word means includes: i. means for producing condition signals, ii. means for storing a plurality of interruption data words in digital form responsive to said receiver being disabled for transferring a selected one of the words onto the bus, and iii. means responsive to the condition signals for selecting the particular interruption data word.

Claim 5

A peripheral unit as recited in claim 3 wherein the bus contains a plurality of priority interruption wires, each wire corresponding to one of a plurality of priority levels, said priority interruption signal transmitting means comprising: i. a priority register for storing a priority number in response to another control signal and selected data signals on the bus, ii. a gated decoder responsive to an input gating signal for converting the contents of said priority register into a signal on a corresponding priority interruption wire, and iii. means for producing the input gating signal.

Claim 6

A peripheral unit as recited in claim 4 wherein the digital computer system additionally includes a memory unit comprising a plurality of addressed locations, the signals from said interruption data word means being grouped to indicate a function to be performed and an address in the memory unit.

Claim 7

A peripheral unit as recited in claim 5 wherein the central processor unit includes means for generating data and control signals for enabling and inhibiting the transmission of priority interruption signals onto the bus and wherein said peripheral unit additionally includes enabling means connected to said priority interruption signal transmitting means to enable or disable said priority interruption signal transmitting means in response to the predetermined enabling and inhibiting data and control signals.

Claim 8

A central processor unit for use in a digital computer system with a central processor unit, and a plurality of peripheral units and an input/output bus with control and data lines connected to said processor and the peripheral units, each peripheral unit having means for transmitting priority interruption signals over one of a plurality of interruption signal wires in the bus, said central processor unit comprising: A. priority determining means connected to the priority interruption wires for selecting a priority interruption signal including means for transmitting selected channel signals corresponding to the priority level being granted onto predetermined bus wires, B. a priority request circuit including: i. a clock enabled by said priority determining means, ii. means responsive to a first pulse from said clock for producing a request synchronizing signal on a bus control wire, and iii. means responsive to a subsequent pulse from said clock for producing an input granting signal on another bus control wire, and C. a priority interruption instruction circuit responsive to completion of said processing in said priority request circuit and conditions in said central processor unit fOr receiving data on the bus wires for use in subsequent central processor unit operations.

Claim 9

A central processor unit for use in a digital computer system with a central processor unit, and a plurality of peripheral units and an input/output bus with control and data lines connected to said processor and the peripheral units, each peripheral unit having means for transmitting priority interruption signals over one of a plurality of interruption signal wires in the bus, said central processor unit comprising: A. priority determining means connected to the priority interruption wires for selecting a priority interruption signal including means for transmitting selected channel signals corresponding to the priority level being granted onto predetermined bus wires, B. a priority request circuit including: i. a clock enabled by said priority determining means, ii. means responsive to a first pulse from said clock for producing a request synchronizing signal on a bus control wire, and iii. means responsive to a subsequent pulse from said clock for producing an input granting signal on another bus control wire, and C. a priority interruption instruction circuit responsive to completion of said processing in said priority request circuit and conditions in said central processor unit fOr receiving data on the bus wires for use in subsequent central processor unit operations.

Claim 10

A central processor unit as recited in claim 7 wherein received signals on certain bus wires define a function, said central processor unit additionally comprising: A. a function register responsive to said clock for storing the function signals, and B. means responsive to data in said function register for generating internal control signals for use by said central processor unit.

Claim 11

A processor as recited in claim 8 wherein said priority request circuit includes termination means responsive to another pulse from said clock for disabling said clock and for indicating said priority request circuit has processed the priority interruption signal, said termination means including: a. a counter driven by said clock, b. means monitoring signals on the function data lines, and c. means responsive to signals from said counter and said monitoring means for enabling said termination means.

Claim 12

A central processor unit as recited in claim 9 wherein said priority interruption instruction circuit comprises: i. first means for synchronizing said circuit to normal central processor unit instruction operations, and ii. means responsive to said first means and the end of an instruction operation for enabling said priority interruption instruction circuit.

Claim 13

A central processor unit as recited in claim 10 wherein said priority determining means includes an input channel for each priority level, each input channel including means for disabling itself.

Claim 14

A digital computer system comprising: A. a bus having control and data wires, B. a central processor unit comprising: i. priority determining means connected to first control wires for granting a priority interruption signal, said priority determining means including means for transmitting signals onto first predetermined bus data wires corresponding to the priority level being granted ii. a priority request circuit including a. a clock enabled by said priority determining means, b. means responsive to a first pulse from said clock for transmitting a request synchronizing signal onto a second bus control wire, and c. means responsive to said clock for transmitting an input granting signal onto a third bus control wire, and iii. a priority interruption instruction circuit responsive to completion of a priority interruption request sequence and to conditions in said central processor unit for receiving data on second data lines, and C. a plurality of peripheral units, at least one peripheral unit including: i. means for transmitting a priority interruption signal onto one of said first control wires indicating one of a plurality of priority levels, ii. a comparator connected to said priority interruption signal transmitting means and adapted to receive signals on said first data wires including a granted priority level, said comparator generating an output signal whenever said peripheral unit has requested a priority interruption at the same level of priority being granted, and iii. an input granting signal receiver connected to said third control wire for coupling an input granting signal through said peripheral unit, said receiver being disabled in response to a signal from said comparator and a request synchronizing signal to thereby block the passage the input granting pulse through said peripheral unit, and iv. means for transmitting a digital interruption data word onto the second data wires for transfer to said central processor unit.

Claim 15

A digital computer system comprising: A. a bus having control and data wires, B. a central processor unit comprising: i. priority determining means connected to first control wires for granting a priority interruption signal, said priority determining means including means for transmitting signals onto first predetermined bus data wires corresponding to the priority level being granted ii. a priority request circuit including a. a clock enabled by said priority determining means, b. means responsive to a first pulse from said clock for transmitting a request synchronizing signal onto a second bus control wire, and c. means responsive to said clock for transmitting an input granting signal onto a third bus control wire, and iii. a priority interruption instruction circuit responsive to completion of a priority interruption request sequence and to conditions in said central processor unit for receiving data on second data lines, and C. a plurality of peripheral units, at least one peripheral unit including: i. means for transmitting a priority interruption signal onto one of said first control wires indicating one of a plurality of priority levels, ii. a comparator connected to said priority interruption signal transmitting means and adapted to receive signals on said first data wires including a granted priority level, said comparator generating an output signal whenever said peripheral unit has requested a priority interruption at the same level of priority being granted, and iii. an input granting signal receiver connected to said third control wire for coupling an input granting signal through said peripheral unit, said receiver being disabled in response to a signal from said comparator and a request synchronizing signal to thereby block the passage the input granting pulse through said peripheral unit, and iv. means for transmitting a digital interruption data word onto the second data wires for transfer to said central processor unit.

Claim 16

A digital computer system as recited in claim 12 wherein said bus contains a plurality of said first control wires, said priority interruption signal transmitting means in said peripheral unit comprising: a. a priority register for storing a priority number in response to signals on a fourth control wire and selected data signals on predetermined data lines, b. a gAted decoder responsive to an input gating signal for converting the contents of said priority register into a signal on a corresponding one of said first control lines, and c. means for producing the input gating signal.

Claim 17

A digital computer system as recited in claim 13 wherein: A. said peripheral unit additionally comprises i. means for generating condition signals. ii. means for storing a plurality of digital interruption data words being responsive to said receiver being disabled for transmitting a selected one of the words over said bus, and iii. means responsive to the condition signals for selecting the digital interruption data word to be transmitted, and B. said central processor unit comprising: i. a function register responsive to said clock for storing portions of the digital interruption data word, and ii. means responsive to the data in said function register for producing control signals for use by said central processor unit.

Claim 18

A digital computer system as recited in claim 14 wherein said input granting receivers in each peripheral unit are connected in series, said input granting signal from said central processor unit being coupled to a first receiver, said system additionally comprising a fifth bus control wire being connected to receive a signal passed through the last peripheral unit, said priority request circuit including termination means in said central processor unit responsive to said clock for disabling said clock to thereby indicate said priority request circuit has processed a priority interruption signal, said termination means including: A. a counter driven by said clock, B. means monitoring the function signals, C. means responsive to signals from said counter, said monitoring means and said fifth wire for enabling said termination means.

Claim 19

A digital computer system as recited in claim 15 additionally including a memory unit comprising a plurality of addressed locations, said signals from said digital interruption data word means being grouped indicating a function to be performed and an address in said memory unit, said priority interruption instruction circuit additionally comprising: a. first means synchronizing said circuit to normal central processor unit instruction operations, and b. means responsive to said first means and the end of an instruction operation for enabling said priority interruption instruction circuit.

Claim 20

A digital computer system as recited in claim 16 wherein i. said priority interruption signal transmitting means in each of said peripheral units includes enabling means responsive to predetermined data and control signals for inhibiting a transfer of priority interruption signals onto said first control wires, and ii. said priority determining means in said central processor unit additionally including an input channel for each priority level, each input channel including means for disabling itself.