Abstract The invention relates to a computer in which control means provide for high speed context switching. In a more specific aspect, the invention involves an arithmetic unit in which a workspace pointer register and control means operable on an interrupt store the contents of the workspace pointer in an element of a workspace in memory designated by the interrupt program and store in the workspace pointer register the address of the first element of the interrupt program workspace. A first register stores the address of a first element of a set of dedicated workspace elements in main memory. A second register stores the memory address of a current instruction of a problem program. A third register maintains current the status of execution of the problem program of which said instruction forms a part; and Workspace for the problem program is the set of workspace elements referenced by the contents of the first register, and upon occurrence of an interrupt, a new workspace is utilized to store the contents of the registers for the problem program permitting return to the problem program by shifting to the registers the contents stored in memory.
A digital computer system providing flexibility in the high-speed selection and utilization of a plurality of multielement workspaces in main memory, comprising: a. a workspace pointer register to store the address of the first of a set of consecutive memory locations forming workspace in main memory; b. a program counter register to store the address of the current program instruction being executed; c. a status register to store a current indication of the status of the program being executed; d. control memory means to supply a distination code to be added to the contents of the workspace pointer register to form the distination address; e. an arithmetic logic unit which sums the destination code with the contents of the workspace pointer register; f. an address register to store the output of the arithmetic logic unit; and g. means to store the address of the first element of a prior workspace at the destination address in response to an interrupt condition.
Claim 2
Dependent Claim
160 words
A digital computer system providing flexibility in the high-speed selection and utilization of a plurality of multielement workspaces in main memory, comprising: a. a workspace pointer register to store the address of the first of a set of consecutive memory locations forming workspace in main memory; b. a program counter register to store the address of the current program instruction being executed; c. a status register to store a current indication of the status of the program being executed; d. control memory means to supply a distination code to be added to the contents of the workspace pointer register to form the distination address; e. an arithmetic logic unit which sums the destination code with the contents of the workspace pointer register; f. an address register to store the output of the arithmetic logic unit; and g. means to store the address of the first element of a prior workspace at the destination address in response to an interrupt condition.
Claim 3
Dependent Claim
53 words
The computer system of claim 1 wherein the storing means further include means for storing the address of the next program instruction of a prior program and the address of an indication of the status of the prior program in a second and third destination address, respectively, in response to an interrupt condition.
Claim 4
Dependent Claim
69 words
The computer system of claim 2 further including: h. return command means, activated upon the conclusion of the interrupt condition, for returning the address of the first element of a prior workspace, the address of the next instruction of the prior program, and the address of an indication of the status of the prior program to the workspace pointer register, the program counter register and the status register, respectively.