US6189140B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Debug interface including logic generating handshake signals between a processor, an input/output port, and a trace logic
Assignee: Advanced Micro Devices Inc
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Filing: 1998-03-04
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Granted: 2001-02-13
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Expires: 2018-03-04
Abstract
Abstract A system for debugging a processor includes a debug interface including a handshake logic for communicating commands and data from a serial input/output port to a processor and to a trace control logic with a low delay. The handshake logic results in a low latency through the inclusion of a state machine that operates at the same speed as the processor. The state machine generates handshake signals to communicate among the serial input/output port, the processor, and the trace control logic.
Inventors
- 👤 Venkateswara Rao Madduri
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:16
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/3698; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/362; G06F11/3632; G06F11/3636; G06F11/3648; G06F11/3656; G06F11/22; G06F11/26; G06F11/261
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
157 words
A processor including a debug interface for interfacing to an external debug device, the processor comprising: a processor core; a serial input/output port coupled to the processor core and communicating information between the external debug device and the processor core; a trace logic accessing trace information indicating instruction execution flow in the processor core; a debug interface coupled to the processor core, the serial input/output port, and the trace logic, the debug interface including a handshake logic generating handshake signals controlling communications between the serial input/output port and the processor core and between the trace logic and the processor core, the handshake logic including a synchronization block synchronizing the handshake signals; a debug register; and a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine including an access debug register state responsive to a command from the processor core to request access to the debug register.
Claim 2
Dependent Claim
157 words
A processor including a debug interface for interfacing to an external debug device, the processor comprising: a processor core; a serial input/output port coupled to the processor core and communicating information between the external debug device and the processor core; a trace logic accessing trace information indicating instruction execution flow in the processor core; a debug interface coupled to the processor core, the serial input/output port, and the trace logic, the debug interface including a handshake logic generating handshake signals controlling communications between the serial input/output port and the processor core and between the trace logic and the processor core, the handshake logic including a synchronization block synchronizing the handshake signals; a debug register; and a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine including an access debug register state responsive to a command from the processor core to request access to the debug register.
Claim 3
Dependent Claim
54 words
A processor according to claim 1 further comprising: a parallel input/output port coupled to the processor core and coupled to the debug interface and communicating information between an external device and the processor core, wherein the debug interface handshake logic generates handshake signals controlling communications between the parallel input/output port and the processor core.
Claim 4
Dependent Claim
18 words
A processor according to claim 1 wherein: the handshake logic includes two condition flags and a register interface.
Claim 5
Dependent Claim
55 words
A processor according to claim 1 further comprising: a debug port state machine coupled to the debug register and the processor interface state machine, and connectable to the debug device, the debug port state machine including a write debug register state responsive to the request to access the debug register by writing the debug register.
Claim 6
Dependent Claim
105 words
A debug interface for interfacing a processor, including a processor core, to a debug device, the debug interface comprising: a serial input/output port; a trace logic coupled to the serial input/output port; and an interface logic coupled to the serial input/output port and coupled to the trace logic, the interface logic generating handshake signals to communicate data between the serial input/output port, the trace logic, and the processor core, the interface logic including a synchronization block for synchronizing the handshake signals and wherein operations of the serial input/output port, the trace logic, and the processor core operate mutually independently and at mutually independent clock rates.
Claim 7
Dependent Claim
105 words
A debug interface for interfacing a processor, including a processor core, to a debug device, the debug interface comprising: a serial input/output port; a trace logic coupled to the serial input/output port; and an interface logic coupled to the serial input/output port and coupled to the trace logic, the interface logic generating handshake signals to communicate data between the serial input/output port, the trace logic, and the processor core, the interface logic including a synchronization block for synchronizing the handshake signals and wherein operations of the serial input/output port, the trace logic, and the processor core operate mutually independently and at mutually independent clock rates.
Claim 8
Dependent Claim
25 words
A debug interface according to claim 5 , further comprising: operations of the serial input/output port, the trace logic, and the processor core operate concurrently.
Claim 9
Dependent Claim
47 words
A debug interface according to claim 5 , further comprising: a parallel input/output port, coupled to the trace logic and coupled to the interface logic, the interface logic including a state machine for communicating commands among the parallel input/output port, the trace logic, and the processor core.
Claim 10
Dependent Claim
55 words
A debug interface according to claim 5 , wherein the interface logic further comprises: a first state machine coupled to the processor core and a second state machine coupled to the debug device, the first and second state machines mutually generating handshake signals controlling a handshake communication between the processor core and the debug device.
Claim 11
Dependent Claim
66 words
A debug interface according to claim 5 , further comprising: a decoder coupled to the interface logic, wherein the interface logic includes a state machine that has a plurality of states including: a command state for receiving written commands from the debug device; a decode state for passing the written commands to the decoder; and a wait state for waiting until a command communication is complete.
Claim 12
Dependent Claim
22 words
A debug interface according to claim 5 , wherein the serial input/output port is a JTAG (Joint Test Action Group) standard port.
Claim 13
Dependent Claim
16 words
A debug interface according to claim 5 , wherein the debug device is a host system.
Claim 14
Dependent Claim
54 words
A debug interface according to claim 5 , further comprising: a decoder coupled to the interface logic, wherein the interface logic includes a state machine that reads commands and data from the serial input/output port and the trace logic, and the decoder decodes commands read from the serial input/output port and the trace logic.
Claim 15
Dependent Claim
99 words
A debug interface according to claim 5 , further comprising: a parallel input/output port, coupled to the trace logic and coupled to the interface logic, the interface logic including a state machine for communicating commands among the parallel input/output port, the trace logic, and the processor core; and a decoder coupled to the interface logic, wherein the interface logic includes a state machine that reads commands and data from the parallel input/output port, serial input/output port and the trace logic, and the decoder decodes commands read from the parallel input/output port, the serial input/output port and the trace logic.
Claim 16
Dependent Claim
55 words
A debug interface according to claim 5 further comprising: a debug register; and a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine including an access debug register state responsive to a command from the processor core to request access to the debug register.
Claim 17
Dependent Claim
102 words
A debug interface according to claim 5 further comprising: a debug register; a processor interface state machine coupled to the debug register and connectable to the processor core, the processor interface state machine including an access debug register state responsive to a command from the processor core to request access to the debug register; and a debug port state machine coupled to the debug register and the processor interface state machine, and connectable to the debug device, the debug port state machine including a write debug register state responsive to the request to access the debug register by writing the debug register.
Claim 18
Dependent Claim
20 words
A debug interface according to claim 5 wherein the debug interface and the processor are disposed on an integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-13 | 2004-08-14 | 2005-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-13 | 2008-08-14 | 2009-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-13 | 2012-08-14 | 2013-02-13 | $7700.00 | Window Closed / Lapsed |