US5615331A
Expired / Lapsed
US
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System and method for debugging a computing system
Assignee: Phoenix Technologies Ltd
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Filing: 1994-06-23
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Granted: 1997-03-25
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Expires: 2014-06-23
Abstract
Abstract A system and method for debugging a development computing system is disclosed. The BIOS in the development system includes a debug engine. Interrupt-handling macros in BIOS include an entry macro to direct debug output codes (e.g., port 80 and beep codes) to the debug engine. A near entry macro is added to BIOS-segment macros (e.g., F000 segment) which provides the offset of the debug engine. A far entry macro is added to non-BIOS-segment macros which provides the segment and offset of the debug engine. The debug engine sends the output codes to a remote host computer via a communication channel (e.g., a bi-directional parallel port) on the development system. The debug engine also saves the contents of various registers on the development system to the host computer. Thus, the invention can be used in a stackelss environment. Debug commands (e.g., memory dump, set break address) can be issued from the host computer to the development system via the communications channel. Such commands are executed on the development system in accordance with program instructions in the debug engine. Debug data associated with the development system may be sent to the host computer via the communications channel in response to a debug command (e.g., memory dump data). Thus, a user can interactively and remotely debug the development system.
Inventors
- 👤 Arman Toorians
- 👤 Elizabeth Q. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:24
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/3698
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
84 words
In a development computing system having a processor and a memory with an interrupt-handling portion, a computer-implemented method for processing debug codes in the development system, the method comprising the steps of: receiving, at a host computer operatively coupled to the development computing system, a debug code generated by the development computing system for processing by the processor; and directing the debug code from the host computer to a debug program located in the interrupt-handling portion of the memory of the development computing system.
Claim 2
Dependent Claim
84 words
In a development computing system having a processor and a memory with an interrupt-handling portion, a computer-implemented method for processing debug codes in the development system, the method comprising the steps of: receiving, at a host computer operatively coupled to the development computing system, a debug code generated by the development computing system for processing by the processor; and directing the debug code from the host computer to a debug program located in the interrupt-handling portion of the memory of the development computing system.
Claim 3
Dependent Claim
15 words
The computer-implemented method of claim 1 wherein the debug code comprises a port 80 code.
Claim 4
Dependent Claim
14 words
The computer-implemented method of claim 1 wherein the debug code comprises a beep code.
Claim 5
Dependent Claim
29 words
The computer-implemented method of claim 1 wherein the debug code is directed to the debug program according to an entry program located in the interrupt-handling portion of the memory.
Claim 6
Dependent Claim
23 words
The computer-implemented method of claim 4 wherein the debug program corresponds to a memory location and the entry program provides the memory location.
Claim 7
Dependent Claim
23 words
The computer-implemented method of claim 4 wherein the debug program corresponds to a memory offset and the entry program provides the memory offset.
Claim 8
Dependent Claim
27 words
The computer-implemented method of claim 4 wherein the debug program corresponds to a segment and offset in memory and the entry program provides the segment and offset.
Claim 9
Dependent Claim
14 words
The computer-implemented method of claim 1 wherein the memory comprises read only memory (ROM).
Claim 10
Dependent Claim
19 words
The computer-implemented method of claim 1 wherein the interrupt-handling portion of the memory comprises a basic input/output system (BIOS).
Claim 11
Dependent Claim
20 words
The computer-implemented method of claim 1 wherein the interrupt-handling portion of the memory is in a ROM BIOS computer chip.
Claim 12
Dependent Claim
44 words
The computer-implemented method of claim 1 further comprising the step of: directing the debug code to a host computer for debugging the development system, wherein the debug program directs the debug code to the host computer via a communication channel in the development system.
Claim 13
Dependent Claim
19 words
The computer-implemented method of claim 11 wherein the communication channel comprises a bi-directional parallel port in the development system.
Claim 14
Dependent Claim
18 words
The computer-implemented method of claim 11 wherein the communication channel comprises a serial port in the development system.
Claim 15
Dependent Claim
27 words
The computer-implemented method of claim 11 further comprising step of: saving the contents of registers in the development system on the host computer via the communication channel.
Claim 16
Dependent Claim
32 words
The computer-implemented method of claim 14 further comprising step of: restoring the contents of the registers in the development system from the host computer to the development system via the communication channel.
Claim 17
Dependent Claim
41 words
The computer-implemented method of claim 11 further comprising steps of: receiving a debug command for processing by the processor in accordance with instructions in the debug program, wherein the debug command is received from the host computer via the communications channel.
Claim 18
Dependent Claim
25 words
The computer-implemented method of claim 16 further comprising steps of: executing the debug command on the processor in accordance with instructions in the debug program.
Claim 19
Dependent Claim
37 words
The computer-implemented method of claim 17 further comprising steps of: sending information associated with the development system to the host computer from the development system via the communication channel in response to execution of the debug command.
Claim 20
Dependent Claim
99 words
In a development computing system having a processor and a memory with an interrupt-handling portion, a computer-implemented method for debugging the development system, the method comprising the steps of: receiving a debug command from a host computer via a communications channel; directing the debug command to a debug program located in the interrupt-handling portion of memory; executing the debug command on the processor in accordance with instructions in the debug program; and sending information associated with the development system to the host computer from the development system via the communication channel in response to execution of the debug command.
Claim 21
Dependent Claim
99 words
In a development computing system having a processor and a memory with an interrupt-handling portion, a computer-implemented method for debugging the development system, the method comprising the steps of: receiving a debug command from a host computer via a communications channel; directing the debug command to a debug program located in the interrupt-handling portion of memory; executing the debug command on the processor in accordance with instructions in the debug program; and sending information associated with the development system to the host computer from the development system via the communication channel in response to execution of the debug command.
Claim 22
Dependent Claim
51 words
The computer-implemented method of claim 19 further comprising the steps of: saving the contents of registers in the development system on the host computer via the communication channel; and restoring the contents of the registers in the development system from the host computer to the development system via the communication channel.
Claim 23
Independent Claim
121 words
A system for debugging a development computing system, the system comprising: a processor in the development system, for executing program instructions; a communication channel, coupled to the processor, for sending and receiving data; a host computer, communicatively coupled to the processor via the communication channel; and memory in the development system, coupled to the processor, for storing instructions for execution by the processor, wherein the memory comprises an interrupt-handling module of program instructions executable on the processor for handling interrupts issued by the development system, and wherein the interrupt-handling module of memory further comprises a debug module of program instructions executable on the processor for receiving interrupt information and for sending such information to the host computer via the communication channel.
Claim 24
Independent Claim
121 words
A system for debugging a development computing system, the system comprising: a processor in the development system, for executing program instructions; a communication channel, coupled to the processor, for sending and receiving data; a host computer, communicatively coupled to the processor via the communication channel; and memory in the development system, coupled to the processor, for storing instructions for execution by the processor, wherein the memory comprises an interrupt-handling module of program instructions executable on the processor for handling interrupts issued by the development system, and wherein the interrupt-handling module of memory further comprises a debug module of program instructions executable on the processor for receiving interrupt information and for sending such information to the host computer via the communication channel.
Claim 25
Dependent Claim
18 words
The system of claim 21 wherein the communication channel comprises a bi-directional parallel port in the development system.
Claim 26
Dependent Claim
17 words
The system of claim 21 wherein the communication channel comprises a serial port in the development system.
Claim 27
Dependent Claim
28 words
The system of claim 21 wherein the host computer comprises debug software, and the host computer sends a debug command to the development system via the communication channel.
Claim 28
Dependent Claim
29 words
The system of claim 24 wherein the processor in the development system executes the debug command on the processor according to program instructions in the debug module of memory.
Claim 29
Dependent Claim
31 words
The system in claim 25 wherein data associated with the development system is sent to the host computer via the communication channel in response to the execution of the debug command.
Claim 30
Dependent Claim
13 words
The system in claim 21 wherein the memory comprises read only memory (ROM).
Claim 31
Dependent Claim
15 words
The system of claim 21 wherein the interrupt-handling module comprises a basic input/output system (BIOS).
Claim 32
Dependent Claim
16 words
The system of claim 21 wherein the interrupt-handling module is in a ROM BIOS computer chip.
Claim 33
Dependent Claim
36 words
The system of claim 21 wherein the development system further comprises at least one register having contents that are saved on the host computer via the communication channel according to program instructions in the debug module.
Claim 34
Dependent Claim
34 words
The system of claim 30 wherein the contents of said register are restored to the development system from the host computer via the communication channel according to the program instructions in the debug module.
Claim 35
Dependent Claim
29 words
The system of claim 21 wherein the interrupt-handling module comprises an entry module of program instructions executable on the processor for directing the interrupt information to the debug module.
Claim 36
Dependent Claim
14 words
The system of claim 21 wherein the interrupt information comprises a port 80 code.
Claim 37
Dependent Claim
13 words
The system of claim 21 wherein the interrupt information comprises a beep code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |