← Back to Patent Explorer
US5943498A Expired / Lapsed US ⏱️ 0.0 years remaining

Microprocessor, method for transmitting signals between the microprocessor and debugging tools, and method for tracing

Assignee: Toshiba Corp
•
Filing: 1995-12-28
•
Granted: 1999-08-24
•
Expires: 2015-12-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A system provides debugging functions for high-speed processors by adding a comparatively small amount of hardware to the microprocessor. A debugging module which receives part of the debugging function is placed in a microprocessor and is connected with a debugging tool outside the processor. In the debugging module, a processor core in the processor accesses and executes a monitor program in the debugging tool 60 through the debugging module. In the normal mode, while the processor executes a user program, the debugging module receives trace information and sends it to the debugging tool and also performs tasks related to the breakpoints.

Inventors

  • 👤 Tatsuo Yano
  • 👤 Takashi Miyamori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 00:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3656; G06F11/3636

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 84 words
In a debugging system for debugging an application program for a microprocessor, said microprocessor comprising: first logic means comprising a debug module for running a monitor program accessed via a dedicated debut interface from a monitor memory in a debugging tool located outside said microprocessor; second logic means comprising a processor core for controlling execution of a user program containing hardware breakpoints; and third logic means for tracing said user program and for providing trace information via said debut module to said debugging tool.
Claim 2
Dependent Claim 84 words
In a debugging system for debugging an application program for a microprocessor, said microprocessor comprising: first logic means comprising a debug module for running a monitor program accessed via a dedicated debut interface from a monitor memory in a debugging tool located outside said microprocessor; second logic means comprising a processor core for controlling execution of a user program containing hardware breakpoints; and third logic means for tracing said user program and for providing trace information via said debut module to said debugging tool.
Claim 3
Dependent Claim 115 words
A tracing method for handling signals between a microprocessor and a debugging tool located outside said microprocessor, comprising the steps of: in case the microprocessor has: a. executed an instruction at a preset address, b. accessed data at a preset address, c. written preset data at a preset address, or d. read preset data from a preset address, sensing occurrence of any events a-d in said debugging tool via a signal pin coupling said microprocessor and said debugging tool and dedicated to signal transmissions between said microprocessor and said debugging tool; and upon such occurrence, deciding the timing of a start or stop of storing trace information into a trace memory of said debugging tool.
Claim 4
Dependent Claim 115 words
A tracing method for handling signals between a microprocessor and a debugging tool located outside said microprocessor, comprising the steps of: in case the microprocessor has: a. executed an instruction at a preset address, b. accessed data at a preset address, c. written preset data at a preset address, or d. read preset data from a preset address, sensing occurrence of any events a-d in said debugging tool via a signal pin coupling said microprocessor and said debugging tool and dedicated to signal transmissions between said microprocessor and said debugging tool; and upon such occurrence, deciding the timing of a start or stop of storing trace information into a trace memory of said debugging tool.

References Cited (Backward Citations)

US4463421A Cited
US4644469A Cited
US4630195A Cited
US4970641A Cited
US4788683A Cited
EP0271910A2 Cited
GB2200482A Cited
US5263153A Cited
US5084814A Cited
EP0313848B1 Cited
US5345580A Cited
US5592677A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-08-23 2003-02-22 2003-08-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-08-23 2007-02-22 2007-08-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-08-23 2011-02-22 2011-08-24 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag