EP0313848B1
Expired / Lapsed
EP
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Data processor with development support features
Assignee: Motorola Solutions Inc
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Filing: 1988-09-29
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Granted: 1994-08-10
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Expires: 2008-09-29
Abstract
No abstract record available.
Inventors
- 👤 John J. Vaglica
- 👤 Jay A. Hartvigsen
- 👤 Rand L. Gray
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F9/30003; G06F9/3005; G06F9/32; G06F9/322; G06F9/323; G06F11/22; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
334 words
An integrated circuit data processor comprising: a central processing unit (11), the central processing unit comprising: (i) a program counter means (PC) for storing an address; (ii) an execution means (52,53,54) for executing a first plurality of instructions while in a first operating mode, for executing a second plurality of instructions while in a second operating mode, for producing instruction prefetch requests, for determining a sequence of instruction execution and for storing addresses in the program counter means in accordance with the sequence; and (iii) a bus controller means (50) for coupling the central processing unit to a bus (12) and for operating the bus as a bus master, in response to one of the instruction prefetch requests from the execution means, to obtain one of said first plurality of instructions from a location in a memory specified by the address stored in the program counter means; and a plurality of resources (13,14,15,16) coupled to the bus, said plurality of resources being under control of the central processing unit for performing a predetermined plurality of functions while in the first operating mode, the predetermined plurality of functions comprises substantially all of the functions which the data processor is capable of performing; said integrated circuit data processor characterised by further comprising: a serial communication bus means (55) coupled to the execution means for providing one of said second plurality of instructions to the execution means under control of an external serial bus master, the serial communication bus means not being operative for serial communication while in the first operating mode; and wherein the execution means (52,53,54) ceases to produce the instruction prefetch requests while in the second operating mode, ceases to determine the sequence of instruction execution while in the second operating mode and ceases to store addresses in the program counter means (PC) in accordance with the sequence while in the second operating mode; and the plurality of resources (13,14,15,16) performs each of said predetermined plurality of functions while in the second operating mode.
Claim 2
Dependent Claim
38 words
An integrated circuit data processor according to claim 1 wherein: the serial communication bus means (55) is operative while in the first mode of operation to provide an output indicating a current activity of the central processing unit.
Claim 3
Dependent Claim
89 words
An integrated circuit data processor according to claim 1 wherein: the central processing unit further comprises: instruction pipe means (51) under control of the execution means for storing instructions obtained by the bus controller means (50) while in the first mode of operation and instructions provided by the serial communication bus means (55) while in the second mode of operation; and the serial communication bus means (55) is operative in while in the first mode of operation to provide an output indicating an activity of the instruction pipe means.
Claim 4
Dependent Claim
61 words
An integrated circuit data processor according to claim 3 wherein: the serial communication bus means (55) is operative while in the first mode of operation to provide a first output (IPIPE/DSO) indicating an advancement of the instruction pipe means and to provide a second output (IFETCH/DSI) to indicate that a current operation of the parallel communication bus is an instruction prefetch.
References Cited (Backward Citations)
No citation records indexed.
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