Serial/parallel input/output bus for microprocessor system

Claim 2

A microprocessor system including: a central processing unit constructed in a single semiconductor integrated circuit, and having a bidirectional parallel multiplexed address/data port and a plurality of control lines, a memory having an address input and a data input/output connected to said port, operation of the memory being under control of said control lines, peripheral means having terminals connected to said port, operation of the I/O unit being under control of said control lines, wherein said central processing unit is controlled by instruction codes fetched from said memory via said port, said instruction codes consisting of a set of instructions, and some of said instruction codes causing the central processing unit to fetch data and addresses from said memory via said port, characterized in that said central processing unit contains a shift register and upon receipt of a certain one of said instructions said shift register is connected either in serial or in parallel to said port thereby functioning to transfer data out of said port by plural bit serial or by plural bit parallel, wherein selection between plural bit serial and plural bit parallel is made by a bit in an address fetched from said memory and applied to said port prior to said data, transfer.

Claim 3

A system according to claim 1 wherein said port has a given number of parallel lines, one of said parallel lines defining the single bit transfer path into said integrated circuit, and a different one of said parallel lines defining the single bit transfer path out of said integrated circuit.

Claim 4

A system according to claim 2 wherein said central processing unit includes an arithmetic logic unit, a plurality of registers, control means for defining operation in response to said instruction codes, and clock means for shifting said shift register one bit position at a time for serial transfer of said data from said port.

Claim 5

A microprocessor device comprising: an arithmetic logic unit having inputs and an output for performing operations on data supplied to said inputs to produce a result at said output according to first control signals, register means for storing data, an input/output port for transferring data and addresses to or from the device, interconnecting bus means within the device for coupling data and addresses to or from the inputs and output of the arithmetic logic unit, said register means, and said input/output port according to second control signals, control means having an input connected to said bus means and generating said first and second control signals in response to instruction words received from said port by said interconnecting means to thereby cause the device to execute a set of instructions, said instruction words being obtained by sending an address out on said port and receiving an instruction word on said port, and shift register means in said device connected to said port via said bus means for transferring data as plural bits to or from said input/output port in serial or parallel and means coupling an address from one of said register means to said input/output port prior to transferring said data, wherein selection of serial or parallel is made by the bit contents of said address.

Claim 6

A microprocessor device comprising: an arithmetic logic unit having inputs and an output for performing operations on data supplied to said inputs to produce a result at said output according to first control signals, register means for storing data, an input/output port for transferring data and addresses to or from the device, interconnecting bus means within the device for coupling data and addresses to or from the inputs and output of the arithmetic logic unit, said register means, and said input/output port according to second control signals, control means having an input connected to said bus means and generating said first and second control signals in response to instruction words received from said port by said interconnecting means to thereby cause the device to execute a set of instructions, said instruction words being obtained by sending an address out on said port and receiving an instruction word on said port, and shift register means in said device connected to said port via said bus means for transferring data as plural bits to or from said input/output port in serial or parallel and means coupling an address from one of said register means to said input/output port prior to transferring said data, wherein selection of serial or parallel is made by the bit contents of said address.

Claim 7

A device according to claim 4 wherein the input/output port is a parallel address/data port.

Claim 8

A device according to claim 5 wherein said port is bidirectional and has multiplexed addresses and data.

Claim 9

A device according to claim 6 wherein one line of said port is an input and a different line is an output when transferring plural bits in serial.

Claim 10

A device according to claim 4 wherein said device is constructed in a single semiconductor integrated circuit.

Claim 11

A device according to claim 8 wherein the same instruction in said set of instructions is used for transferring plural bits in serial as is used for transferring plural bits in parallel.