US5764885A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for tracing data flows in high-speed computer systems
Assignee: Hewlett Packard Development Co LP
•
Filing: 1994-12-19
•
Granted: 1998-06-09
•
Expires: 2014-12-19
Abstract
Abstract A data flow of a processor is traced while accessing data stored in a memory and in a plurality of registers during operation of the processor. The tracing involves detecting an unpredictable accessing of data on the assumption that a predictable accessing can be reconstructed without any further input. The unpredictable accessing is identified by setting and clearing a trace bit associated with each of the registers according to identifying the accessing as direct memory-to-register, register-to-register, constant-to-register, and indirect memory. If a trace bit is set on a register storing data being used as a base address during the indirect memory acceding, data flow control information, such as the base address stored in the register being used during the indirect acceding is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and a copy of the data having an initial state can be examined to analyze the data flows during the real-time operation of the processor.
Inventors
- 👤 Richard L. Sites
- 👤 Sharon E. Perl
- 👤 G. Michael Uhler
- 👤 David G. Conroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:40
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
151 words
An apparatus for tracing data flows during an operation of a processor comprising: a memory storing a data structure having an initial state, the data structure including addresses, the addresses for accessing data of the data structures; a plurality of registers storing the data while the data structure is manipulated by the processor, wherein each of the plurality of registers further includes a trace bit; means for accessing the data stored in the memory and in the plurality of registers; means, coupled to the means for accessing, for detecting an unpredictable accessing of the data; means for propagating the trace bit from a source register to a destination resister during an accessing of the data; and means, responsive to the unpredictable accessing of the data, for recording information related to the unpredictable accessing of the data to trace the data flows while the data structure is being manipulated by the processor.
Claim 2
Independent Claim
151 words
An apparatus for tracing data flows during an operation of a processor comprising: a memory storing a data structure having an initial state, the data structure including addresses, the addresses for accessing data of the data structures; a plurality of registers storing the data while the data structure is manipulated by the processor, wherein each of the plurality of registers further includes a trace bit; means for accessing the data stored in the memory and in the plurality of registers; means, coupled to the means for accessing, for detecting an unpredictable accessing of the data; means for propagating the trace bit from a source register to a destination resister during an accessing of the data; and means, responsive to the unpredictable accessing of the data, for recording information related to the unpredictable accessing of the data to trace the data flows while the data structure is being manipulated by the processor.
Claim 3
Dependent Claim
101 words
The apparatus as in claim 1 further comprising: means for identifying the accessing of the data as direct memory-to-register, register-to-register, constant-to-register, and indirect memory; means for setting the trace bit of the register receiving the data during the direct memory-to-register accessing; means for clearing the trace bit of the register receiving the data during the constant-to-register accessing; means for recording the data of the register being used to determine an indirect address of the data structure during the indirect memory accessing if the trace bit of the register being used to determine the indirect address of the data structure is set.
Claim 4
Dependent Claim
33 words
The apparatus as in claim 2 further comprising: means, responsive to the information being recorded, for clearing the trace bit of the register being used to determine the indirect address of the memory.
Claim 5
Dependent Claim
34 words
The apparatus as in claim 1 further comprising: means for recording a time of an occurrence of the unpredictable accessing of the data with the information related to the unpredictable accessing of the data.
Claim 6
Dependent Claim
100 words
The apparatus as in claim 1 further comprising: a queue storing the information related to the unpredictable accessing of the data, the queue having a plurality of entries, each entry storing the information for an occurrence of the unpredictable accessing of the data; a driver reading the information stored in the plurality of entries of the queue; a trace buffer connected to a port of the processor, the port communicating the information read by the driver from the queue to the trace buffer, the port communicating the information at a rate determined by a clock signal generated by the processor.
Claim 7
Dependent Claim
75 words
The apparatus as in claim 1 further comprising: a queue storing the information related to the unpredictable accessing of the data, the queue having a plurality of entries, each entry storing the information for an occurrence of the unpredictable accessing of the data; means for signaling when the queue is full; and means, in response to a signal which indicates that the queue is full, for communicating the information from the queue to the memory.
Claim 8
Dependent Claim
17 words
The apparatus as in claim 5 wherein the trace buffer is an allocated portion of the memory.
Claim 9
Dependent Claim
58 words
The apparatus as in claim 5 further comprising: means for accessing a copy of the data structure having the initial state; means for reading the information stored in the trace buffer; and means for processing the copy of the data structure according the information to reconstruct the data flows as they were during the operation of the processor.
Claim 10
Dependent Claim
56 words
The apparatus as in claim 5 further comprising: means for accessing a copy of the data structure having the initial state; means for reading the information stored in the trace buffer; and means for processing the copy of the data structure according the information while accessing the data structure to analyze the data flows in real-time.
Claim 11
Dependent Claim
50 words
The apparatus as in claim 1 wherein the memory includes a virtual memory storing the data structure at a plurality of address spaces; means for detecting a context switch of the plurality of address spaces; and means, responsive to the context switch, for recording information related to the context switch.
Claim 12
Dependent Claim
25 words
The apparatus as in claim 10 wherein the information related to the context switch is an identifier of one of the plurality of address spaces.
Claim 13
Independent Claim
108 words
A method for tracing data flows during an operation of a processor comprising: storing a data structure having an initial state in a memory, the data structure including addresses, the addresses for accessing data of the data structures; storing the data in a plurality of registers while the data structure is manipulated by the processor; accessing the data stored in the memory and in the plurality of registers; detecting an unpredictable accessing of the data; and in response to detecting the unpredictable accessing, recording information related to the unpredictable accessing of the data to trace the data flows while the data structure is being manipulated by the processor.
Claim 14
Independent Claim
108 words
A method for tracing data flows during an operation of a processor comprising: storing a data structure having an initial state in a memory, the data structure including addresses, the addresses for accessing data of the data structures; storing the data in a plurality of registers while the data structure is manipulated by the processor; accessing the data stored in the memory and in the plurality of registers; detecting an unpredictable accessing of the data; and in response to detecting the unpredictable accessing, recording information related to the unpredictable accessing of the data to trace the data flows while the data structure is being manipulated by the processor.
Claim 15
Dependent Claim
128 words
The method as in claim 12 further comprising: identifying the accessing of the data as direct memory-to-register, register-to-register, constant-to-register, and indirect memory; setting the trace bit of the register to receive the data during the direct memory-to-register accessing; propagating the trace bit from the register being used as a source of the data to the trace bit of the register being used as a destination of the data during the register-to-register accessing; clearing the trace bit of the register receiving the data during the constant-to-register accessing; recording the data of the register being used to determine an indirect address of the data structure during the indirect memory accessing if the trace bit of the register being used to determine the indirect address of the data structure is set.
Claim 16
Dependent Claim
32 words
The method as in claim 13 further comprising: in responsive to the information being recorded, clearing the trace bit of the register being used to determine the indirect address of the memory.
Claim 17
Dependent Claim
32 words
The method as in claim 12 further comprising: recording a time of an occurrence of the unpredictable accessing of the data with the information related to the unpredictable accessing of the data.
Claim 18
Dependent Claim
90 words
The method as in claim 12 further comprising: storing the information related to the unpredictable accessing of the data in a queue, the queue having a plurality of entries, each entry storing the information for an occurrence of the unpredictable accessing of the data; reading the information stored in the plurality of entries of the queue with a driver; communicating the information read by the driver from the queue to a trace buffer, the port communicating the information at a rate determined by a clock signal generated by the processor.
Claim 19
Dependent Claim
72 words
The method as in claim 12 further comprising: storing the information related to the unpredictable accessing of the data in a queue, the queue having a plurality of entries, each entry storing the information for an occurrence of the unpredictable accessing of the data; signaling when the queue is full; and in response to a signal which indicates that the queue is full, communicating the information from the queue to the memory.
Claim 20
Dependent Claim
18 words
The method as in claim 16 further comprising: allocating a portion of the memory as the trace buffer.
Claim 21
Dependent Claim
52 words
The method as in claim 16 further comprising: accessing a copy of the data structure having the initial state; reading the information stored in the trace buffer; and processing the copy of the data structure according the information to reconstruct the data flows as they were during the operation of the processor.
Claim 22
Dependent Claim
50 words
The method as in claim 16 further comprising: accessing a copy of the data structure having the initial state; reading the information stored in the trace buffer; and processing the copy of the data structure according the information while accessing the data structure to analyze the data flows in real-time.
Claim 23
Dependent Claim
47 words
The method as in claim 12 wherein the memory includes a virtual memory storing the data structure at a plurality of address spaces; detecting a context switch of the plurality of address spaces; and in response to the context switch, recording information related to the context switch.
Claim 24
Dependent Claim
25 words
The method as in claim 21 wherein the information related to the context switch is an identifier of one of the plurality of address spaces.
Claim 25
Independent Claim
79 words
An apparatus for tracing a data flow while accessing a data structure stored in a memory connected to a processor comprising: means for detecting an unpredictable accessing of the data structure by the processor inaccording with data accessing instructions of the processor, the means for detecting being independent of detecting an execution flow of the processor; and means, responsive to the unpredictable accessing of the data structure, for recording information related to the unpredictable accessing of the data structure.
Claim 26
Independent Claim
79 words
An apparatus for tracing a data flow while accessing a data structure stored in a memory connected to a processor comprising: means for detecting an unpredictable accessing of the data structure by the processor inaccording with data accessing instructions of the processor, the means for detecting being independent of detecting an execution flow of the processor; and means, responsive to the unpredictable accessing of the data structure, for recording information related to the unpredictable accessing of the data structure.
References Cited (Backward Citations)
US3659272A
Cited
US3707725A
Cited
US4812964A
Cited
US5535331A
Cited
US5127103A
Cited
US5058114A
Cited
US5274811A
Cited
US5206948A
Cited
US5564028A
Cited
US5488688A
Cited
US5446876A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-08 | 2001-12-08 | 2002-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-08 | 2005-12-08 | 2006-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-08 | 2009-12-08 | 2010-06-09 | $7700.00 | Window Closed / Lapsed |