US5535331A
Expired / Lapsed
US
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Processor condition sensing circuits, systems and methods
Assignee: Texas Instruments Inc
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Filing: 1992-02-03
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Granted: 1996-07-09
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Expires: 2012-02-03
Abstract
Abstract Operations of a data processing device are traced by detecting a jump address in the program counter sequence, and pushing the jump address onto a trace stack.
Inventors
- 👤 Gary L. Swoboda
- 👤 Peter N. Ehlig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/318555; G06F11/22; G06F11/2205; G06F11/2221; G06F11/2236; G06F11/2289; G06F11/26; G06F11/261; G06F11/263; G06F11/267; G06F11/27; G06F11/3636; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7842; G06F15/786; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F8/00; G06F8/40; G06F8/41; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30021; G06F9/30072; G06F9/30094; G06F9/30098; G06F9/30101; G06F9/30141; G06F9/34; G06F9/35; G06F9/46; G06F9/461; G06F9/462; G01R31/31701; G01R31/318505; G06F11/006; G06F11/273; G06F11/2733; G06F11/30; G06F11/3003; G06F11/3024; G06F11/3055; G06F11/3089; G06F11/3093; G06F11/32; G06F11/34
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
78 words
A data processing device comprising: a program counter, a program counter stack, a trace stack and means for causing the program counter to count through a series of addresses; and a control circuit for entering a jump address into said program counter in substitution for a current address in the series, thereby establishing a discontinuity, said control circuit including means for pushing the current address onto the program counter stack and the jump address onto the trace stack.
Claim 2
Dependent Claim
78 words
A data processing device comprising: a program counter, a program counter stack, a trace stack and means for causing the program counter to count through a series of addresses; and a control circuit for entering a jump address into said program counter in substitution for a current address in the series, thereby establishing a discontinuity, said control circuit including means for pushing the current address onto the program counter stack and the jump address onto the trace stack.
Claim 3
Dependent Claim
23 words
The data processing device of claim 1 wherein said control circuit includes means for pushing the current address onto the trace stack also.
Claim 4
Dependent Claim
55 words
The data processing device of claim 1 further comprising an interrupt circuit connected to said control circuit and memory means for storing an interrupt routine, said control circuit responsive to the memory means and comprising means also operative upon completion of the interrupt routine for popping the program counter stack and pushing the trace stack.
Claim 5
Dependent Claim
38 words
The data processing device of claim 3 wherein, upon completion of the interrupt routine, the trace stack is pushed with a most recently accessed address of the interrupt routine and a return address from which operations were interrupted.
Claim 6
Dependent Claim
123 words
A data processing device, comprising: a program counter for holding an address of an instruction currently being processed by said data processing device; means for causing said program counter ordinarily to count through a continuous sequence of addresses; a control circuit for entering into said program counter an out-of-sequence address that establishes within the sequence of program counter addresses an address discontinuity defined by the out-of-sequence address and the address which immediately preceded the out-of-sequence address in the program counter; a program counter stack, and means for selectively pushing an address from said program counter onto said program counter stack; and a trace stack, said control circuit including means responsive to the address discontinuity for pushing the out-of-sequence address onto said trace stack.
Claim 7
Dependent Claim
123 words
A data processing device, comprising: a program counter for holding an address of an instruction currently being processed by said data processing device; means for causing said program counter ordinarily to count through a continuous sequence of addresses; a control circuit for entering into said program counter an out-of-sequence address that establishes within the sequence of program counter addresses an address discontinuity defined by the out-of-sequence address and the address which immediately preceded the out-of-sequence address in the program counter; a program counter stack, and means for selectively pushing an address from said program counter onto said program counter stack; and a trace stack, said control circuit including means responsive to the address discontinuity for pushing the out-of-sequence address onto said trace stack.
Claim 8
Dependent Claim
31 words
The data processing device of claim 5, wherein said control circuit includes means for permitting only those program counter addresses that define address discontinuities to be pushed onto said trace stack.
Claim 9
Dependent Claim
31 words
The data processing device of claim 6, wherein said control circuit includes means for causing every program counter address which defines an address discontinuity to be pushed onto said trace stack.
Claim 10
Dependent Claim
25 words
The data processing device of claim 5, including a serial scan circuit interconnected with said trace stack and accessible externally of said data processing device.
Claim 11
Dependent Claim
39 words
The data processing device of claim 8, wherein said trace stack is connected in series with said serial scan circuit to define therewith a serial scan path for permitting external access to the addresses stored in said trace stack.
Claim 12
Dependent Claim
33 words
The data processing device of claim 9, wherein said control circuit includes means for generating a state vector representing whether or not a particular address in said trace stack is a jump address.
Claim 13
Dependent Claim
39 words
The data processing device of claim 10, including a shift register operatively associated with said trace stack for storing said state vector, said shift register being located in said serial scan path for permitting external access to said vector.
Claim 14
Dependent Claim
40 words
The data processing device of claim 11, wherein said shift register is arranged to permit serial shifting of said state vector out of said shift register along a signal path which is separate and distinct from said serial scan path.
Claim 15
Dependent Claim
27 words
The data processing device of claim 12, including means connected to said signal path for examining said state vector to determine when said trace stack is full.
Claim 16
Independent Claim
113 words
A method of tracing operations of a data processing device having a program counter which normally counts through a continuous sequence of addresses at which instructions to be processed by the data processing device reside, comprising the steps of: providing the data processing device with a trace stack which is separate from a program counter stack of the data processing device; determining whether a program counter address is an out-of-sequence address that establishes within the sequence of program counter addresses an address discontinuity defined by the out-of-sequence address and the address which immediately precedes the out-of-sequence address; and responding to a detected address discontinuity by pushing the out-of-sequence address onto the trace stack.
Claim 17
Independent Claim
113 words
A method of tracing operations of a data processing device having a program counter which normally counts through a continuous sequence of addresses at which instructions to be processed by the data processing device reside, comprising the steps of: providing the data processing device with a trace stack which is separate from a program counter stack of the data processing device; determining whether a program counter address is an out-of-sequence address that establishes within the sequence of program counter addresses an address discontinuity defined by the out-of-sequence address and the address which immediately precedes the out-of-sequence address; and responding to a detected address discontinuity by pushing the out-of-sequence address onto the trace stack.
Claim 18
Dependent Claim
26 words
The method of claim 14, including the step of permitting only those program counter addresses that define address discontinuities to be pushed onto the trace stack.
Claim 19
Dependent Claim
23 words
The method of claim 15, including the step of pushing onto the trace stack every program counter address that defines an address discontinuity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-09 | 2000-01-08 | 2000-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-09 | 2004-01-08 | 2004-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-09 | 2008-01-08 | 2008-07-09 | $7700.00 | Window Closed / Lapsed |