Real-time tracing of dynamic local data in high level languages in the presence of process context switches

Claim 2

Apparatus for aiding in debugging of real-time programs executing on a target processor, which programs do not contain special trace instructions, comprising: a. means for capturing inputs to and outputs from the target processor; and b. means for real-time tracing of values of at least one local variable referenced in one of the programs, using the inputs to and outputs from the target processor, during a process context switch on the target processor, which process context switch involves the at least one local variable.

Claim 3

The apparatus of claim 1 wherein the inputs to and outputs from the target processor comprise address, data, and status signals appearing on pins of the target processor.

Claim 4

The apparatus of claim 1 wherein the capturing means comprises a clamp for placing over a chip which contains the target processor, the clamp including a plurality of inputs for coupling with respective pins of the chip and reading data therefrom substantially without disturbing the operations of the target processor.

Claim 5

The apparatus of claim 1 wherein the means for tracing comprises means for deducing a stack frame pointer of the program from the inputs and outputs.

Claim 6

The apparatus of claim 4 wherein the means for deducing comprises means for recognizing standard machine instructions of the target processor.

Claim 7

The apparatus of claim 5 wherein the standard machine instructions comprise an instruction which restores, from a memory coupled with the target processor, a plurality of register values one of which values is the stack frame pointer.

Claim 8

The apparatus of claim 6 wherein the the instruction is a moveml-type instruction.

Claim 9

The apparatus of claim 5 wherein the standard machine instructions comprise an instruction which restores from a memory coupled with the target processor a register value which is the stack frame pointer.

Claim 10

The apparatus of claim 8 wherein the instruction is a movel-type instruction.

Claim 11

The apparatus of claim 5 wherein the standard machine instructions comprise an instruction which creates a stack frame for storing local data belonging to a local procedure.

Claim 12

The apparatus of claim 10 wherein the instruction is a link-type instruction.

Claim 13

The apparatus of claim 5 wherein the standard machine instructions comprise a second instruction which removes the stack frame.

Claim 14

The apparatus of claim 12 wherein the second instruction is an unlink-type instruction.

Claim 15

The apparatus of claim 1 wherein: a. the inputs t and outputs from the target processor comprise address, data, and status signals appearing on pins of the target processor; and b. the tracing means comprises: i. a local tag memory for storing an image of tag information which represents a selection by a user of which local data to trace; ii. means for deducing a stack frame pointer of the program from the address, data and status signals; iii. means for storing a base address corresponding to a location of tag information in the local tag memory; iv. means for locating the tag information within the local tag memory using the base address and an offset which corresponds to a difference between the stack frame pointer and an address captured by the capturing means.

Claim 16

The apparatus of claim 14 wherein: a. the program comprises a plurality of procedures, each call to one of the procedures corresponding to a respective stack frame; b. the image represents the selection by the user of local data to trace from more than one of the procedures, whereby the local tag memory contains a plurality of sets of tag information relating to respective procedure stack frames; c. the means for storing the base address stores a plurality of base addresses one for each set of tag information; d. the means for locating uses as the base address one of the start addresses which corresponds to a procedure which includes the address captured by the capturing means, whereby parallel means for locating for each of the procedures of the program are eliminated.

Claim 17

The apparatus of claim 1 comprising means or real-time ignoring machine instructions which are prefetched and not executed.

Claim 18

The apparatus of claim 16 wherein the ignoring means comprises a global tag memory; means for setting a basic block bit in the global tab memory corresponding to each instruction in an object code representation of the program; and means for sensing a value of a basic block bit corresponding to an instruction after a prefetched instruction to determine whether the prefetched instruction should be ignored.

Claim 19

The apparatus of claim 1 comprising a host processor which comprises a. means for storing source code for the program; b. means for compiling the source code, the compiling means supplying an object code representation of the program and a symbol table; and c. means for downloading the object code representation into the target processor.

Claim 20

The apparatus of claim 18 wherein the symbol table comprises: a. start and end addresses of procedures of the program; b. offsets of local data locations; and c. addresses of instructions which begin basic blocks.

Claim 21

The apparatus of claim 19 wherein the host processor further comprises: a. means for accepting a selection by a user of local data in the program to be traced; and b. means for displaying trace results.

Claim 22

The apparatus of claim 20 wherein the selection further comprises an indication of whether the local data is to be traced on write references only or on read and write references.

Claim 23

The apparatus of claim 20 wherein the host processor comprises: means for deriving from the symbol table a set of procedure code bounds which comprises the respective start and end addresses of the procedures in which local data are to be traced.

Claim 24

The apparatus of claim 22 wherein the host processor further comprises means for deriving from the symbol table, an image of contents of a global memory, the image comprising basic block bits that are set to indicate instructions that begin basic blocks.

Claim 25

The apparatus of claim 23 wherein I. the tracing means comprises: a. input means for receiving data derived from the symbol table and the selection from the host processor; b. second means for capturing a frame pointer of the program from the inputs and outputs of the target processor, by decoding op-codes of the program, which op-codes are captured by the means for capturing; c. a local tag table memory for storing the selection, the local tag table memory having addressable locations and an output for supplying an indication of whether a particular local datum is part of the selection; and d. logic means for determining, from: i) the set of procedure code bounds; ii) the frame pointer, and iii) address and data information appearing in the inputs and outputs of the target processor, whether control in the target processor is currently in a given procedure and for specifying a given one of the locations in the local tag table memory which corresponds to the local datum within the given procedure; and II. the capturing means provides values of the local data in the selection under the control of the local tag table memory.

Claim 26

The apparatus of claim 24 wherein the determining means comprises a plurality of pairs of registered comparators, each pair of registered comparators containing respective upper and lower procedure code bounds, the registered comparators being loaded from the set of procedure code bounds.

Claim 27

The apparatus of claim 24 wherein the second capturing means comprises: a. input means for receiving a plurality of flags indicating: i. whether an instruction which affects the stack frame pointer is present on a data bus of the target processor (link, unlink, movem); ii. which register of the target processor contains the frame pointer (S 10 , S 11 , S 12 ); iii. whether signals on the data bus represent an instruction (FCO); iv. whether an instruction fetch appearing on the pins is part of a prefetch only; and v. which fetch in a move multiple instruction is for the frame pointer register (S3, S2, S1, S0); b. logic for steering signals captured from the data bus and an address bus of the target processor, the steering logic having i. an input for receiving signals captured from the data and addresses buses; and ii. an output; c. a frame pointer register, having i. an input at the output of the steering logic, and ii. a control input, the frame pointer register loading a value of the frame pointer from the steering logic under control of a signal received at the control input; and d. a state machine for converting the plurality of flags into a second plurality of flags indicating whether: i. the steering logic should provide at its output, signals from the address bus; ii. the steering logic should provide at its output, signals from the data bus; iii. to load the frame pointer register from the steering logic; and iv. the frame pointer register contains a valid frame pointer.

Claim 28

Apparatus for aiding in debugging of a real-time program executing on a target processor, the program comprising a plurality of procedures, each call to one of the procedures corresponding to a respective stack frame, the apparatus comprising: a. means for capturing inputs to and outputs from the target processor; b. means (120) for receiving: a selection by a user of local data to be traced, the local data to be traced being from a plurality of procedures; and data derived from a symbol table generated on a host processor as a result of compilation of a source-code version of the program; c. second means for capturing a frame pointer of the program from the inputs and outputs from the target processor, by decoding op-codes of the program, which op codes are captured by the means for capturing; d. a local tag table memory for storing the selection, the local tag table memory having addressable locations and an output for supplying an indication of whether a particular local datum is part of the selection, the local tag memory containing a plurality of sets of tag information relating to respective procedure stack frames; and e. logic means for specifying, based on the inputs and outputs, the data derived from the symbol table, and the frame pointer, a given one of the locations in the local tag table memory which corresponds to the local datum within the given procedure, using a segmented addressing scheme; wherein the capturing means provides values of the local data in the selection under the control of the local tag table memory.

Claim 29

Apparatus for aiding in debugging of a real-time program executing on a target processor, the program comprising a plurality of procedures, each call to one of the procedures corresponding to a respective stack frame, the apparatus comprising: a. means for capturing inputs to and outputs from the target processor; b. means (120) for receiving: a selection by a user of local data to be traced, the local data to be traced being from a plurality of procedures; and data derived from a symbol table generated on a host processor as a result of compilation of a source-code version of the program; c. second means for capturing a frame pointer of the program from the inputs and outputs from the target processor, by decoding op-codes of the program, which op codes are captured by the means for capturing; d. a local tag table memory for storing the selection, the local tag table memory having addressable locations and an output for supplying an indication of whether a particular local datum is part of the selection, the local tag memory containing a plurality of sets of tag information relating to respective procedure stack frames; and e. logic means for specifying, based on the inputs and outputs, the data derived from the symbol table, and the frame pointer, a given one of the locations in the local tag table memory which corresponds to the local datum within the given procedure, using a segmented addressing scheme; wherein the capturing means provides values of the local data in the selection under the control of the local tag table memory.

Claim 32

The method of claim 28 further comprising, after the decoding step, the step of a) if the decoded op code is one which can change the stack frame pointer, checking whether a corresponding instruction is being executed by checking a tag bit of a next instruction; and b) if the corresponding instruction is not being executed, ignoring the corresponding instruction as prefetched and not executed.

Claim 33

The method of claim 29 further comprising, after the checking step, the step of: a) if the decoded op code is a movem, further decoding the corresponding instruction to determine if the frame pointer is modified.