US5446876A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware mechanism for instruction/data address tracing
Assignee: International Business Machines Corp
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Filing: 1994-04-15
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Granted: 1995-08-29
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Expires: 2014-04-15
Abstract
Abstract An improved instruction tracing mechanism provides a combination of hardware, internal to the CPU, and novel software. Additional registers are added to interconnected to the CPU. These registers store values indicating the instruction address, data address, whether the instruction was a load or store, the number of bytes moved and whether any address mapping changes occurred. The registers are read by a trace interrupt handler which then provides the information to a trace buffer and a profile buffer. The end user can then access the trace and profile information through the input/output (I/O) system of the data processing system.
Inventors
- 👤 Frank E. Levine
- 👤 Brian C. Twichell
- 👤 Edward H. Welbon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
73 words
A method of recording trace information relating to the execution of instructions on a processor unit, comprising the steps of: storing instruction information output from at least one execution unit in said processing unit; determining from said instruction information whether said instructions access data from a memory subsystem; and determining from said instruction information, stored in said processor unit, a data address at which said data, operated on by said instructions, was accessed.
Claim 2
Independent Claim
73 words
A method of recording trace information relating to the execution of instructions on a processor unit, comprising the steps of: storing instruction information output from at least one execution unit in said processing unit; determining from said instruction information whether said instructions access data from a memory subsystem; and determining from said instruction information, stored in said processor unit, a data address at which said data, operated on by said instructions, was accessed.
Claim 3
Dependent Claim
38 words
A method according to claim 1 wherein said step of determining whether said instructions access data, comprises the step of determining a quantity of data accessed from said memory location, and for storing said quantity as trace information.
Claim 4
Dependent Claim
49 words
A method according to claim 2 wherein said step of determining a data address comprises the steps of: mapping said data address to a physical location in said memory subsystem; and mapping an instruction address at which said instructions were accessed to a physical location in said memory subsystem.
Claim 5
Dependent Claim
32 words
A method according to claim 3 further comprising the step of determining from said instruction information if any of said instructions, executing on said processing unit, have altered said means for mapping.
Claim 6
Dependent Claim
31 words
A method according to claim 4 wherein said step of determining if said instructions have been altered comprises the step of storing alterations to said means for mapping as trace information.
Claim 7
Dependent Claim
32 words
A method according to claim 5 wherein said step of determining whether said instructions access data comprises the step of determining whether said instructions are a load instruction or a store instruction.
Claim 8
Dependent Claim
77 words
A processor unit that records trace information relating to the execution of instructions on said processor unit, comprising: means for storing instruction information output from at least one execution unit in said processing unit; means for determining from said instruction information whether said instructions access data from a memory subsystem; and means for determining from said instruction information, stored in said processor unit, a data address at which said data, operated on by said instructions, was accessed.
Claim 9
Dependent Claim
77 words
A processor unit that records trace information relating to the execution of instructions on said processor unit, comprising: means for storing instruction information output from at least one execution unit in said processing unit; means for determining from said instruction information whether said instructions access data from a memory subsystem; and means for determining from said instruction information, stored in said processor unit, a data address at which said data, operated on by said instructions, was accessed.
Claim 10
Dependent Claim
37 words
A system according to claim 7 wherein said means for determining whether said instructions access data, comprises means for determining a quantity of data accessed from said memory location, and for storing said quantity as trace information.
Claim 11
Dependent Claim
50 words
A system according to claim 8 wherein said means for determining a data address comprises: means for mapping said data address to a physical location in said memory subsystem; and means for mapping an instruction address at which said instructions were accessed to a physical location in said memory subsystem.
Claim 12
Dependent Claim
31 words
A system according to claim 9 further comprising means for determining from said instruction information if any of said instructions, executing on said processing unit, have altered said means for mapping.
Claim 13
Dependent Claim
30 words
A system according to claim 10 wherein said means for determining if said instructions have been altered comprises means for storing alterations to said means for mapping as trace information.
Claim 14
Dependent Claim
31 words
A system according to claim 11 wherein said means for determining whether said instructions access data comprises means for determining whether said instructions are a load instruction or a store instruction.
Claim 15
Dependent Claim
30 words
A system according to claim 12 further comprising means for recreating said instructions which have previously executed on said processing unit from said means for mapping and said trace information.
Claim 16
Dependent Claim
27 words
A system according to claim 13 wherein said means for storing comprises a plurality of registers connected to the output of said at least one execution unit.
Claim 17
Dependent Claim
16 words
A system according to claim 14 wherein said means for mapping comprises a look up table.
Claim 18
Dependent Claim
27 words
A system according to claim 15 further comprising: buffer means for storing said trace information; and means, connected to said buffer means, for outputting said trace information.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |