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EP0270983A2
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Method for the parallel simulation of multiprocessor computer systems
Assignee: International Business Machines Corp
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Filing: 1987-12-01
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Granted: —
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Expires: 2007-12-01
Abstract
Abstract A method for speeding up the simulation of the execution of parallel programs running on multiprocessor (MP) systems. It provides a user with the performance statistics and MP traces of parallel programs. These can further be used to study in detail the characteristics, memory access patterns of parallel programs, or to drive a memory-network simulation model of an MP system. The method comprises breaking the sequential process of MP simulation into a group of cooperating processes running on a multiprogrammed system with each process simulating one processor. The processes are very independent of each other, therefore a speedup of simulation is achieved if the multiprogrammed system is itself running on an MP system.
Inventors
- 👤 Frederica Darema-Rogers
- 👤 David Alson George
- 👤 Evelyn Au Melton
- 👤 Vern Alan Norton
- 👤 Gregory Francis Pfister
- 👤 Kimming So
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 08:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F11/00; G06F11/30; G06F11/34; G06F11/3457; G06F11/3461; G06F30/00; G06F30/20
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
166 words
Method for the parallel simulation of a multiprocessor computing system on a base system including at least one CPU, a main memory, an operating system resident in said system which provides for multiprogrammed operation of said system whereby a plurality of jobs or programs may execute concurrently, said operating system including a further resident memory management facility allowing said plurality of programs to allocate commonly writable shared segments in said memory, characterized by the steps of: providing in the system a separate sequential simulating program for each CPU of the multiprocessor being simulated, providing in the system a separate I/O device for each simulating program in the base system to produce a uniprocessor trace for that simulating program, providing in the system for the recording of synchronization events in the uniprocessor traces to record where and when one processor must wait for the execution of an instruction(s) of one or more other processors to be completed before proceeding with the execution of its own task sequence.
Claim 2
Dependent Claim
166 words
Method for the parallel simulation of a multiprocessor computing system on a base system including at least one CPU, a main memory, an operating system resident in said system which provides for multiprogrammed operation of said system whereby a plurality of jobs or programs may execute concurrently, said operating system including a further resident memory management facility allowing said plurality of programs to allocate commonly writable shared segments in said memory, characterized by the steps of: providing in the system a separate sequential simulating program for each CPU of the multiprocessor being simulated, providing in the system a separate I/O device for each simulating program in the base system to produce a uniprocessor trace for that simulating program, providing in the system for the recording of synchronization events in the uniprocessor traces to record where and when one processor must wait for the execution of an instruction(s) of one or more other processors to be completed before proceeding with the execution of its own task sequence.
Claim 3
Dependent Claim
34 words
A method for the parallel simulation of a multiprocessor computer system as set forth in Claim 1 including: providing in the individual simulating programs a facility for executing atomic instructions in the base system.
Claim 4
Dependent Claim
50 words
A method for the parallel simulation of a multiprocessor computer system as set forth in Claim 2 including: utilizing said atomic instructions in the simulating programs which are directly executable on the base system to maintain the proper sequencing of memory access to shared memory space between the simulated processors.
Claim 5
Independent Claim
51 words
A method for the parallel simulation of a multiprocessor computer system as set forth in one of the Claims 1-3 wherein the base computer system includes a multiprogrammed operating system, said method including: running each of said plurality of simulating programs on said base multiprogrammed system as an individual user task.
Claim 6
Dependent Claim
72 words
A method for the parallel simulation of a multiprocessor computer system as set forth in Claim 4 wherein the base computer system is itself a multiprocessor computer system, said method including running the user tasks in parallel on the multiple CPUs of the base system as separate tasks assigned by the multiprogrammed operating system whereby the speed up of the simulation is proportional to the number of processors in the base system.
Claim 7
Dependent Claim
80 words
A method for the parallel simulation of a multiprocessor computer system as set forth in Claim 4 or 5 wherein the step of providing for synchronization events in the simulated system includes: inserting a sequence mark in the application program which is callable at the base system whereby a special synchronization marker is written into affected uniprocessor traces to allow the occurrence of the same marker in two or more traces to be used in processing an overall MP trace.
Claim 8
Independent Claim
82 words
A method for the parallel simulation of a multiprocessor computer system as set forth in one of the Claims 4-6 including: running a multiprocessor application system on top of the simulated CPU, simulating programs and base multiprogrammed system respectively, producing one uniprocessor output trace for each simulating program on its own assigned I/O device, recording synchronization events in the individual output traces as specified, and, producing a final multiprocessor output trace from the individual uniprocessor output traces to align related synchronization events.
Claim 9
Dependent Claim
173 words
Electronic data processing system (the base system) including at least two CPUs, a main memory, and an operating system resident in said system which provides for the concurrent execution of user processes on all of the processors of the base system, characterized in that a facility is provided which allows the high speed simulation of a multiprocessor computer system, including: a facility in said operating system which allows multiprogrammed operation of said system whereby a plurality of said user processes execute as separate programs on said system, a resident memory management facility allowing said plurality of programs to allocate commonly writable shared segments in said memory, a facility in said operating system which provides synchronization instructions for marking synchronization events in output traces produced by said simulation, a separate sequential simulating program for each processor of the multiprocessor being simulated which is adapted to run concurrently on said base system as a separate user task and a multiprocessable application system adapted to run on and be distributed across said plurality of simulating programs.
Claim 10
Dependent Claim
173 words
Electronic data processing system (the base system) including at least two CPUs, a main memory, and an operating system resident in said system which provides for the concurrent execution of user processes on all of the processors of the base system, characterized in that a facility is provided which allows the high speed simulation of a multiprocessor computer system, including: a facility in said operating system which allows multiprogrammed operation of said system whereby a plurality of said user processes execute as separate programs on said system, a resident memory management facility allowing said plurality of programs to allocate commonly writable shared segments in said memory, a facility in said operating system which provides synchronization instructions for marking synchronization events in output traces produced by said simulation, a separate sequential simulating program for each processor of the multiprocessor being simulated which is adapted to run concurrently on said base system as a separate user task and a multiprocessable application system adapted to run on and be distributed across said plurality of simulating programs.
Claim 11
Dependent Claim
50 words
An electronic data processing system adapted for the parallel simulation of a multiprocessor computer system as set forth in Claim 8 including: a separate I/O device dedicated to serving each simulating program connected to said base system for recording a separate output uniprocessor trace as produced by that simulating program.
Claim 12
Dependent Claim
53 words
An electronic data processing system adapted for the parallel simulation of a multiprocessor computer system as set forth in Claim 8 or 9 including: a facility for specifying atomic instructions in a simulating program which are directly executable on the base system whereby accesses to common shared segments of the memory are controlled.
Claim 13
Independent Claim
194 words
A method for performing a parallel simulation of one or more application programs running on a simulated multiprocessor system, said method including: executing, at a base system where the simulation is performed, a simulating program for each processor in the simulated multiprocessor system, each simulating program simulating one processor and storing the trace generated by the simulation on its own dedicated I/O device, so that all of the resources in the base system including a plurality of CPUs may be optimally used, providing for the sharing of data among the simulated processor through a commonly addressable segment in the memory of the base system, and using atomic instructions in the simulating programs to serialize concurrent accesses to shared memory locations in the simulated multiprocessor system, which use is guaranteed by using the same atomic instructions at the base system, and inserting synchronization records into the individual uniprocessor traces by the program as implemented for each simulated CPU whenever it is found that an operation in one simulated CPU is waiting for the completion of an operation in another simulated CPU, whereby any synchronization events among the processors in the simulated multiprocessor system are recorded.
Claim 14
Independent Claim
194 words
A method for performing a parallel simulation of one or more application programs running on a simulated multiprocessor system, said method including: executing, at a base system where the simulation is performed, a simulating program for each processor in the simulated multiprocessor system, each simulating program simulating one processor and storing the trace generated by the simulation on its own dedicated I/O device, so that all of the resources in the base system including a plurality of CPUs may be optimally used, providing for the sharing of data among the simulated processor through a commonly addressable segment in the memory of the base system, and using atomic instructions in the simulating programs to serialize concurrent accesses to shared memory locations in the simulated multiprocessor system, which use is guaranteed by using the same atomic instructions at the base system, and inserting synchronization records into the individual uniprocessor traces by the program as implemented for each simulated CPU whenever it is found that an operation in one simulated CPU is waiting for the completion of an operation in another simulated CPU, whereby any synchronization events among the processors in the simulated multiprocessor system are recorded.
Claim 15
Dependent Claim
48 words
A parallel simulation method as set forth in Claim 11 including: recreating a full multiprocessor trace, for the simulated multiprocessor system with correct execution sequencing from the set of said individual uniprocessor traces each of which is generated by the simulating programs for the various individual simulated multiprocessors.
References Cited (Backward Citations)
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