US4571677A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tracing system
Assignee: Mitsubishi Electric Corp
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Filing: 1982-11-17
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Granted: 1986-02-18
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Expires: 2002-11-17
Abstract
Abstract A tracing system for confirming an instruction which is executed by a central processing unit in accordance with an address of each instruction is provided with an AND gate for controlling such signal indicating coincidence between the address and trace address by utilizing a valid signal indicating that the contents of a memory address register of the central processing unit are true addresses of the instruction to be executed in the next stage.
Inventors
- 👤 Mitsunori Hirayama
- 👤 Kimio Yamanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
188 words
A tracing system wherein a central processing unit compares contents of a memory address register holding an address corresponding to the instruction to be executed in the next execution stage with a trace address which has previously been set to detect coincidence of the trace address by means of the coincidence of said contents of the memory address register and said trace address, said system comprising a trace register holding said trace address which has previously been set; a comparator connected to said trace address register and to said memory address register for comparing the trace address set in said trace address register with the address set in said memory address register to output a coincident signal in the case where said trace address coincides with said memory address; and an AND circuit for receiving the coincident signal derived from said comparator and a valid signal sent from an arithmetic and logic circuit of said central processing unit in the case when the address corresponding to the instruction to be executed in the next execution stage in said central processing unit is held in said memory address register.
Claim 2
Dependent Claim
188 words
A tracing system wherein a central processing unit compares contents of a memory address register holding an address corresponding to the instruction to be executed in the next execution stage with a trace address which has previously been set to detect coincidence of the trace address by means of the coincidence of said contents of the memory address register and said trace address, said system comprising a trace register holding said trace address which has previously been set; a comparator connected to said trace address register and to said memory address register for comparing the trace address set in said trace address register with the address set in said memory address register to output a coincident signal in the case where said trace address coincides with said memory address; and an AND circuit for receiving the coincident signal derived from said comparator and a valid signal sent from an arithmetic and logic circuit of said central processing unit in the case when the address corresponding to the instruction to be executed in the next execution stage in said central processing unit is held in said memory address register.
Claim 3
Dependent Claim
38 words
A tracing system as claimed in claim 1, which further comprises a trace controller means for presetting the next trace address in said trace address register at the time when output signal of said AND circuit is received.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-17 | 1989-08-19 | 1990-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-17 | 1993-08-19 | 1994-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-17 | 1997-08-19 | 1998-02-18 | $7700.00 | Window Closed / Lapsed |