Test apparatus performing runtime replacement of program instructions with breakpoint instructions for processor having multiple instruction fetch capabilities

Claim 2

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle for immediate execution of said retrieved program instructions by said processor, wherein each program instruction is stored in a designated location in said program memory, each said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means, responsive to said processor retrieving a plurality of program instructions from said program memory for immediate execution of the retrieved program instructions by said processor, for comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory address of the last previously retrieved program instruction to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said comparing means, for substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; means for storing said one presently retrieved program instruction; and means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one retrieved program instruction.

Claim 3

The apparatus of claim 1 wherein said predefined program instruction comprises: a breakpoint instruction.

Claim 4

The apparatus of claim 1 further including: means for recording said retrieved program instructions.

Claim 5

The apparatus of claim 3 further including: means for deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 6

The apparatus of claim 1 wherein said substituting means includes: means interposed between said processor and said program memory for transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction.

Claim 7

The apparatus of claim 5 wherein said substituting means further includes: buffer means for storing said one retrieved program instruction.

Claim 8

The apparatus of claim 6 wherein said replacing means includes: means responsive to the execution of said predefined program instruction for reading said intercepted retrieved program instruction from said buffer means to said processor.

Claim 9

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, each said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory address of the last previously retrieved program instruction to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said comparing means, for substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one retrieved program instruction; means for recording said retrieved program instructions; and means for deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 10

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, each said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory address of the last previously retrieved program instruction to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said comparing means, for substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one retrieved program instruction; means for recording said retrieved program instructions; and means for deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 11

The apparatus of claim 8, wherein said predefined program instruction comprises: a breakpoint instruction.

Claim 12

The apparatus of claim 8 wherein said substituting means includes: means interposed between said processor and said program memory for transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction.

Claim 13

The apparatus of claim 10 wherein said substituting means further includes: buffer means for storing said one retrieved program instruction.

Claim 14

The apparatus of claim 11 wherein said replacing means includes: means responsive to the execution of said predefined program instruction for reading said intercepted retrieved program instruction from said buffer means to said processor.

Claim 15

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle for immediate execution of said retrieved program instructions by said processor, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a method of determining a sequence of program instructions executed by said processor comprising the computer implemented steps of: comparing, in response to said processor retrieving a plurality of program instructions from said program memory for immediate execution of the retrieved program instructions by said processor, the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory addresses of the last previously retrieved program instructions to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; storing said one presently retrieved program instruction; and replacing, in response to said processor executing said predefined program instruction, said executed predefined program instruction with said one retrieved program instruction.

Claim 16

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle for immediate execution of said retrieved program instructions by said processor, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a method of determining a sequence of program instructions executed by said processor comprising the computer implemented steps of: comparing, in response to said processor retrieving a plurality of program instructions from said program memory for immediate execution of the retrieved program instructions by said processor, the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory addresses of the last previously retrieved program instructions to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; storing said one presently retrieved program instruction; and replacing, in response to said processor executing said predefined program instruction, said executed predefined program instruction with said one retrieved program instruction.

Claim 17

The method of claim 13 wherein said step of substituting includes the step of transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction.

Claim 18

The method of claim 14 wherein said step of substituting further includes the step of: intercepting said one retrieved program instruction.

Claim 19

The method of claim 15 wherein said step of replacing includes the step of: reading said intercepted retrieved program instruction to said processor in response to said processor executing said predefined program instruction.

Claim 20

The method of claim 13 further including the step of: recording said retrieved program instructions.

Claim 21

The method of claim 17 further including the step of: deleting said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 22

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a method of determining a sequence of program instructions executed by said processor comprising the computer implemented steps of: comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory addresses of the last previously retrieved program instructions to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; replacing, in response to said processor executing said predefined program instruction, said executed predefined program instruction with said one retrieved program instruction; recording said retrieved program instructions; and deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 23

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a method of determining a sequence of program instructions executed by said processor comprising the computer implemented steps of: comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory addresses of the last previously retrieved program instructions to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch; replacing, in response to said processor executing said predefined program instruction, said executed predefined program instruction with said one retrieved program instruction; recording said retrieved program instructions; and deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 24

The method of claim 19 wherein said step of substituting includes the step of transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction.

Claim 25

The method of claim 20 wherein said step of substituting further includes the step of: intercepting said one retrieved program instruction.

Claim 26

The method of claim 21 wherein said step of replacing includes the step of: reading said intercepted retrieved program instruction to said processor in response to said processor executing said predefined program instruction.

Claim 27

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during each program instruction fetch cycle for immediate execution of said retrieved program instructions by said processor, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means, responsive to said processor retrieving a plurality of program instructions from said program memory for immediate execution of the retrieved program instructions by said processor, for intercepting one of said plurality of program instructions retrieved by said processor during a program instruction fetch cycle in response to an out of sequence program instruction fetch; means, responsive to said intercepting means, for substituting a predefined program instruction for said one intercepted program instruction; means for storing said one intercepted program instruction; and means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one intercepted program instruction.

Claim 28

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during each program instruction fetch cycle for immediate execution of said retrieved program instructions by said processor, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means, responsive to said processor retrieving a plurality of program instructions from said program memory for immediate execution of the retrieved program instructions by said processor, for intercepting one of said plurality of program instructions retrieved by said processor during a program instruction fetch cycle in response to an out of sequence program instruction fetch; means, responsive to said intercepting means, for substituting a predefined program instruction for said one intercepted program instruction; means for storing said one intercepted program instruction; and means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one intercepted program instruction.

Claim 29

The apparatus of claim 23 wherein said substituting means includes: means interposed between said processor and said program memory for transmitting said predefined program instruction to said processor in lieu of said one intercepted program instruction.

Claim 30

The apparatus of claim 24 wherein said substituting means further includes: buffer means for storing said one intercepted program instruction.

Claim 31

The apparatus of claim 25 wherein said replacing means includes: means responsive to said processor executing said predefined program instruction for reading said intercepted stored program instruction from said buffer means to said processor.

Claim 32

The apparatus of claim 23 further including: means for recording said retrieved program instructions.

Claim 33

The apparatus of claim 27 further including: means for deleting said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 34

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory address of the last previously retrieved program instruction to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said comparing means, for substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch, including: means, interposed between said processor and said program memory, for transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction, buffer means for intercepting said one retrieved program instruction, means, responsive to said processor executing said predefined program instruction, for replacing said one retrieved program instruction, including: means, responsive to said processor executing said predefined program instruction, for reading said intercepted retrieved program instruction from said buffer means to said processor; means for recording said retrieved program instructions; means for deleting said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 35

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during a program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for comparing the memory address of each of said plurality of program instructions retrieved by said processor during a presently executing program instruction fetch cycle with the memory address of the last previously retrieved program instruction to determine whether said presently retrieved program instructions represent an out of sequence program instruction fetch; means, responsive to said comparing means, for substituting a predefined program instruction for one of said presently retrieved program instructions when said presently retrieved program instructions represent an out of sequence program instruction fetch, including: means, interposed between said processor and said program memory, for transmitting said predefined program instruction to said processor in lieu of said one retrieved program instruction, buffer means for intercepting said one retrieved program instruction, means, responsive to said processor executing said predefined program instruction, for replacing said one retrieved program instruction, including: means, responsive to said processor executing said predefined program instruction, for reading said intercepted retrieved program instruction from said buffer means to said processor; means for recording said retrieved program instructions; means for deleting said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 36

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during each program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for intercepting one of said plurality of program instructions retrieved by said processor during a program instruction fetch cycle in response to an out of sequence program instruction fetch; means, responsive to said intercepting means, for substituting a predefined program instruction for said one intercepted program instruction; means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one intercepted program instruction; means for recording said retrieving program instructions; and means for deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 37

In a test system that monitors the operation of a system under test, which system under test includes a processor that retrieves a plurality of program instructions from a program memory during each program instruction fetch cycle, wherein each program instruction is stored in a designated location in said program memory, said designated location having a memory address, a program instruction trace apparatus for determining a sequence of program instructions executed by said processor comprising: means for intercepting one of said plurality of program instructions retrieved by said processor during a program instruction fetch cycle in response to an out of sequence program instruction fetch; means, responsive to said intercepting means, for substituting a predefined program instruction for said one intercepted program instruction; means, responsive to said processor executing said predefined program instruction, for replacing said executed predefined program instruction with said one intercepted program instruction; means for recording said retrieving program instructions; and means for deleting one or more of said recorded program instructions in said plurality of program instructions retrieved in said one program instruction fetch cycle when said processor fails to execute said predefined program instruction.

Claim 38

The apparatus of claim 30 wherein said substituting means includes: means interposed between said processor and said program memory for transmitting said predefined program instruction to said processor in lieu of said one intercepted program instruction.

Claim 39

The apparatus of claim 31 wherein said substituting means further includes: buffer means for storing said one intercepted program instruction.

Claim 40

The apparatus of claim 32 wherein said replacing means includes: means responsive to said processor executing said predefined program instruction for reading said intercepted stored program instruction from said buffer means to said processor.