US4176394A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for maintaining a history of the most recently executed instructions in a digital computer
Assignee: Unisys Corp
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Filing: 1977-06-13
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Granted: 1979-11-27
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Expires: 1997-06-13
Abstract
Abstract An apparatus for maintaining a history of instructions which have been most recently executed by a digital computer. A push-down stack is utilized for storing the contents of the program address counter, or the operand portion of the instruction register, of the computer upon the execution of every instruction and then pushing down the push-down stack whenever the last instruction executed by the digital computer was a branch type instruction. Provision may also be made for addressing the push-down stack so that the contents thereof may be reviewed in the order opposite from which it was loaded. This apparatus allows a user or diagnostic program to have access to the address of the most recently executed branch type instructions. In this way, a history of the most recently executed instructions can be maintained to aid hardware and software diagnostics.
Inventors
- 👤 David G. Kaminski
- 👤 Mickiel P. Fedde
- 👤 Robert C. DeWard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:48
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0766
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
377 words
In a digital computer capable of executing instructions and of the type having a program address register for holding the address of the next instruction to be executed, said instructions containing a function code portion and an operand address portion and at least one of said instructions being capable of causing a branch to a program address not in succession with the last program address and containing a main memory for storing said instructions, an apparatus for maintaining a history of which of said instructions have been executed by said digital computer, comprising: an instruction register for holding the instruction currently being executed by said digital computer and coupled to said main memory for receiving said instructions from said main memory; decoding means coupled to a portion of said instruction register containing said function code portion for decoding the instruction type and for providing a signal of a first binary significance when the function code portion of said instruction designates a branch instruction and of the opposite binary significance when said function code portion specifies a non-branch instruction; an incrementable program address register coupled to the portion of said instruction register holding said operand address portion for temporarily holding the address of the next instruction to be executed by said digital computer; a set of registers whose data inputs are coupled to the output of said portion of said instruction register containing said operand address portion each of said registers capable of holding the value of the contents of said operand portion of said instructions; an incrementable counter register whose output is coupled to said set of registers for selecting one of said set of registers based upon the value of the contents of said counter registers; and control means coupled to the output of said decoding means and to said set of registers for causing the contents of said operand portion of said instruction register to be stored in the selected one of said set of registers upon the execution of each instruction by said digital computer and for incrementing the value of the contents of said counter register whenever said decoding means produces a signal of said first binary significance; whereby a history is maintained of which of said instructions have been most recently executed.
Claim 2
Dependent Claim
377 words
In a digital computer capable of executing instructions and of the type having a program address register for holding the address of the next instruction to be executed, said instructions containing a function code portion and an operand address portion and at least one of said instructions being capable of causing a branch to a program address not in succession with the last program address and containing a main memory for storing said instructions, an apparatus for maintaining a history of which of said instructions have been executed by said digital computer, comprising: an instruction register for holding the instruction currently being executed by said digital computer and coupled to said main memory for receiving said instructions from said main memory; decoding means coupled to a portion of said instruction register containing said function code portion for decoding the instruction type and for providing a signal of a first binary significance when the function code portion of said instruction designates a branch instruction and of the opposite binary significance when said function code portion specifies a non-branch instruction; an incrementable program address register coupled to the portion of said instruction register holding said operand address portion for temporarily holding the address of the next instruction to be executed by said digital computer; a set of registers whose data inputs are coupled to the output of said portion of said instruction register containing said operand address portion each of said registers capable of holding the value of the contents of said operand portion of said instructions; an incrementable counter register whose output is coupled to said set of registers for selecting one of said set of registers based upon the value of the contents of said counter registers; and control means coupled to the output of said decoding means and to said set of registers for causing the contents of said operand portion of said instruction register to be stored in the selected one of said set of registers upon the execution of each instruction by said digital computer and for incrementing the value of the contents of said counter register whenever said decoding means produces a signal of said first binary significance; whereby a history is maintained of which of said instructions have been most recently executed.
Claim 3
Dependent Claim
73 words
An apparatus as in claim 1 which further comprises: display means coupled to the contents of said set of registers for reading the value of the contents of the selected one of said set of registers; and said control means further including means for decrementing the value contained in said counter register, such that the contents of said set of registers may be reviewed in the reverse order from which they were stored.
Claim 4
Dependent Claim
264 words
In a digital computer capable of executing a series of instructions called a program, in which said instructions are each addressable by a program address register, an apparatus for maintaining the history of which of said instructions in said program have been executed most recently by said digital computer, comprising: a set of registers, each capable of holding the value of the contents of said program address register; a pointer register whose output is connected to said set of registers such that a unique value in said pointer register will uniquely select one of said set of registers; means connected to said program address register and to the input to said set of registers for storing into the selected one of said set of registers, the value of the contents of said program address register for every one of said instructions executed by said digital computer; means coupled to said pointer register for incrementing the value contained in said pointer register whenever the instruction last executed by said digital computer was determined to be a branch instruction; display means coupled to the output of said set of registers for reading the value of the contents of the selected one of said set of registers; and means coupled to said pointer register for decrementing the value contained in said pointer register such that the value of the contents of each of said set of registers may be reviewed in the opposite order from which they were scored; whereby a history is maintained of which of said instructions of said program have been most recently executed.
Claim 5
Dependent Claim
264 words
In a digital computer capable of executing a series of instructions called a program, in which said instructions are each addressable by a program address register, an apparatus for maintaining the history of which of said instructions in said program have been executed most recently by said digital computer, comprising: a set of registers, each capable of holding the value of the contents of said program address register; a pointer register whose output is connected to said set of registers such that a unique value in said pointer register will uniquely select one of said set of registers; means connected to said program address register and to the input to said set of registers for storing into the selected one of said set of registers, the value of the contents of said program address register for every one of said instructions executed by said digital computer; means coupled to said pointer register for incrementing the value contained in said pointer register whenever the instruction last executed by said digital computer was determined to be a branch instruction; display means coupled to the output of said set of registers for reading the value of the contents of the selected one of said set of registers; and means coupled to said pointer register for decrementing the value contained in said pointer register such that the value of the contents of each of said set of registers may be reviewed in the opposite order from which they were scored; whereby a history is maintained of which of said instructions of said program have been most recently executed.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-11-26 | 1983-05-28 | 1983-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-11-26 | 1987-05-28 | 1987-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-11-26 | 1991-05-28 | 1991-11-27 | $7700.00 | Window Closed / Lapsed |