Data processing system auto address development logic for multiword fetch

Claim 1

In a software analyzer connected to a common bus of a data processing system in which a central processor unit (CPU) makes requests for multiple words of information to be transferred between a memory and said CPU and in which said multiple words of information are transferred one word at a time over said common bus during multiple information transfer cycles, an improved address development logic for developing consecutive addresses to be associated with said multiple words, wherein the improvement comprises: A. a synchronous presettable address counter, coupled to said common bus, said address counter having data input for receiving a starting address and data outputs for providing a next address; B. an address register, coupled to said address counter, said address register having data inputs for receiving said next address and data outputs for providing a current address; C. a load means, coupled to said address counter and said common bus, said load means for providing a signal to enable the loading of said address counter with said starting address when said loading means detects the transfer of said starting address during an initial information transfer cycle of said multiple information transfer cycles; D. an early cycle clocking means, coupled to said address counter and said common bus, said early cycle clocking means for providing a signal to said address counter incidating that it is early in an information transfer cycle of said multiple information transfer cycles and that said address counter if load enabled should load said starting address, or if not load enabled said address counter is to compute said next address; and E. a late cycle clocking means, coupled to said early cycle clocking means and said address register, said late cycle clocking means for providing a signal indicating to said address register that it is to load said next address into said address register, said late cycle means producing said clocking signal late in said information transer cycle, whereby during all but said initial transfer cycle in which said starting address is transferred, said address counter is computing the next address while said current address remains available at the outputs of said address register.