EP0525672A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor with program tracing
Assignee: NEC Corp
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Filing: 1992-07-24
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Granted: —
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Expires: 2012-07-24
Abstract
Abstract A microprocessor according to the present invention includes a start detector. The start detector monitors operation of an execution unit, and supplies an instruction step signal to a tracer at each time when an execution start of each instruction is detected thereby. The tracer traces a program executed in the execution unit in accordance with the instruction step signal.
Inventors
- 👤 Tomohisa c/o NEC Corporation Arai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 09:54
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
91 words
A microprocessor, comprising: an execution unit for supplying an address of a required instruction, and executing an instruction in accordance with an instruction code supplied thereto; an internal cache for supplying an instruction code to said execution unit when said address supplied from said execution unit corresponds to an instruction code cached therein; and a start detector for monitoring operation of said execution unit and supplying an instruction step signal to a predetermined tracer at each time when an execution start of each instruction in said execution unit is detected thereby.
Claim 2
Dependent Claim
91 words
A microprocessor, comprising: an execution unit for supplying an address of a required instruction, and executing an instruction in accordance with an instruction code supplied thereto; an internal cache for supplying an instruction code to said execution unit when said address supplied from said execution unit corresponds to an instruction code cached therein; and a start detector for monitoring operation of said execution unit and supplying an instruction step signal to a predetermined tracer at each time when an execution start of each instruction in said execution unit is detected thereby.
Claim 3
Dependent Claim
44 words
A microprocessor, according to claim 1, further comprising: a branch direction detector for detecting a branch direction of a branch instruction in said execution unit, and supplying a branch direction signal, indicating whether said branch instruction is materialized of not, to said predetermined tracer.
Claim 4
Dependent Claim
56 words
A microprocessor, according to claim 2, further comprising: a dynamic branch detector for monitoring occurrence of a dynamic event in said execution unit, so that a present program of said execution unit is branched to a predetermined address and the control is transferred to a trace trap interrupt program when said dynamic event is detected thereby.
Claim 5
Dependent Claim
28 words
A microprocessor, according to claim 1 or 2, wherein: said instruction step signal and said branch direction signal are supplied to said tracer by using external terminals, respectively.
Claim 6
Dependent Claim
35 words
A microprocessor, according to claim 1 or 2, wherein: said instruction step signal and said branch direction signal are encoded and are supplied to said tracer through a status line without using external terminals, respectively.
Claim 7
Dependent Claim
69 words
In a microprocessor including an execution unit and a cache memory, means for informing an exterior unit of an execution to be conducted in accordance a program; means for informing said external unit of a branch direction of a branch instruction to be conducted in accordance with said program; and means for generating an interrupt in case where a flow of said program is not calculated in advance statically.
Claim 8
Dependent Claim
69 words
In a microprocessor including an execution unit and a cache memory, means for informing an exterior unit of an execution to be conducted in accordance a program; means for informing said external unit of a branch direction of a branch instruction to be conducted in accordance with said program; and means for generating an interrupt in case where a flow of said program is not calculated in advance statically.
Claim 9
Dependent Claim
36 words
In a microprocessor including an execution unit and a cache memory, according to claim 8, said execution start informing means including an exclusive use terminal through which said execution start is supplied to said external unit.
Claim 10
Dependent Claim
31 words
In a microprocessor including an execution unit and a cache memory, according to claim 7, said execution use terminal providing a pulse signal thereon, said pulse signal indicating said execution start.
Claim 11
Dependent Claim
36 words
In a microprocessor including an execution unit and a cache memory, according to claim 6, said branch direction informing means including an exclusive use terminal through which said branch direction is supplied to said external unit.
References Cited (Backward Citations)
No citation records indexed.
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