US5058114A
Expired / Lapsed
US
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Program control apparatus incorporating a trace function
Assignee: Hitachi Ltd
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Filing: 1989-03-14
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Granted: 1991-10-15
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Expires: 2009-03-14
Abstract
Abstract In a program control apparatus with a program ROM which forms sequence control signals for executing various control actions according to specified conditions, a memory circuit is provided which is activated during a particular operation mode to successively store information corresponding to the external conditions and also information on times taken by the operation sequence of the program control apparatus.
Inventors
- 👤 Shigeo Kuboki
- 👤 Norihiko Sugimoto
- 👤 Syunji Inada
- 👤 Masahiro Ueno
- 👤 Takeshi Harakawa
- 👤 Kazuhisa Inada
- 👤 Toshihiko Tominaga
- 👤 Yasushi Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/36; G06F11/362; G06F11/3636; G06F11/3466; G06F11/348; G06F11/3409; G06F11/3419; G06F2201/00; G06F2201/88
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
76 words
A digital data communication processor formed on a semiconductor substrate comprising: sequence control means for storing programs that generate sequence control signals to perform various control actions according to specified state and event codes; and memory means operatively associated with said sequence control means for successively storing state and event information corresponding to the specified state and event codes and time information concerning the time spent in an operation sequence depending on the specified state code.
Claim 2
Dependent Claim
76 words
A digital data communication processor formed on a semiconductor substrate comprising: sequence control means for storing programs that generate sequence control signals to perform various control actions according to specified state and event codes; and memory means operatively associated with said sequence control means for successively storing state and event information corresponding to the specified state and event codes and time information concerning the time spent in an operation sequence depending on the specified state code.
Claim 3
Dependent Claim
61 words
The digital data communication processor as set forth in claim 1, wherein the sequence control means comprises decoding means for decoding the specified state and event codes and microprogram memory means for storing microprograms, wherein the microprogram memory means is specified with a start address to generate a series of sequence control signals according to the specified state and event codes.
Claim 4
Dependent Claim
19 words
The digital data communication processor as set forth in claim 2, wherein the memory means is a FIFO memory.
Claim 5
Dependent Claim
24 words
The digital data communication processor as set forth in claim 2, wherein the decoding means and the microprogram memory means are formed of ROM.
Claim 6
Dependent Claim
27 words
The digital data communication processor as set forth in claim 2, wherein at least one of the decoding means and the microprogram memory is formed of RAM.
Claim 7
Dependent Claim
45 words
The digital data communication processor as set forth in claim 2, wherein the state information to be stored in said memory means successively corresponds to current states and the event information to be stored in said memory means corresponds to events which generate state transitions.
Claim 8
Dependent Claim
31 words
The digital data communication processor as set forth in claim 6, wherein the time information to be stored in said memory means includes a real number part and an exponential part.
Claim 9
Dependent Claim
118 words
An error detecting assembly incorporated into a digital data communication processor which is formed on a semiconductor substrate and which includes a microprogram ROM, wherein said microprogram ROM forms sequential control signals for executing selected sequence control operations depending on state and event codes, said error detecting assembly comprising: a memory circuit for successively storing contents including states and event information corresponding to the state and event codes and time information concerning the time spent by a sequence control operation depending on the state code; and, a reading means for reading the contents of said memory circuit wherein the contents of said memory circuit is used to reveal the states through which the sequence control operations have passed.
Claim 10
Dependent Claim
118 words
An error detecting assembly incorporated into a digital data communication processor which is formed on a semiconductor substrate and which includes a microprogram ROM, wherein said microprogram ROM forms sequential control signals for executing selected sequence control operations depending on state and event codes, said error detecting assembly comprising: a memory circuit for successively storing contents including states and event information corresponding to the state and event codes and time information concerning the time spent by a sequence control operation depending on the state code; and, a reading means for reading the contents of said memory circuit wherein the contents of said memory circuit is used to reveal the states through which the sequence control operations have passed.
Claim 11
Dependent Claim
51 words
The error detecting assembly incorporated into the digital data communication processor as set forth in claim 8, wherein said contents of said memory circuit is supplied to a tracing means which is provided outside of said digital data communication processor to trace the state of the sequence control operations executed therein.
Claim 12
Dependent Claim
30 words
The error detecting means incorporated into the digital data communication processor as set forth in claim 9, wherein the time information includes a real number part and an exponential part.
Claim 13
Dependent Claim
51 words
The error detecting assembly incorporated into the digital data communication processor as set forth in claim 8, wherein the state information to be stored in said memory circuit successively corresponds to current states and the event information to be stored in said memory circuit corresponds to events which generate state transitions.
Claim 14
Dependent Claim
135 words
An error detecting method for use in a digital data communication processor formed on a semiconductor substrate, said error detecting method comprising the steps of: operating a microprogram ROM through a plurality of states, wherein said operating forms sequential control operations depending on state and event codes; successively storing information in a memory circuit wherein said information includes state and event information corresponding to the state and event codes and time information concerning the time spent in a sequence control operation depending on the state code; reading the contents of said memory circuit wherein the contents of said memory circuit reveal the states through which the sequence control operations have passed; and, tracing the state of the sequence control operation executed in said digital data communication processor by using the contents of said memory circuit.
Claim 15
Dependent Claim
135 words
An error detecting method for use in a digital data communication processor formed on a semiconductor substrate, said error detecting method comprising the steps of: operating a microprogram ROM through a plurality of states, wherein said operating forms sequential control operations depending on state and event codes; successively storing information in a memory circuit wherein said information includes state and event information corresponding to the state and event codes and time information concerning the time spent in a sequence control operation depending on the state code; reading the contents of said memory circuit wherein the contents of said memory circuit reveal the states through which the sequence control operations have passed; and, tracing the state of the sequence control operation executed in said digital data communication processor by using the contents of said memory circuit.
Claim 16
Dependent Claim
49 words
The error detecting method for use in the digital data communication processor as set forth in claim 12, wherein the state information to be stored in said memory circuit is present state information and the event information to be stored in said memory circuit is state transition event information.
Claim 17
Dependent Claim
31 words
The error detecting method for use in the digital data communication processor as set forth in claim 13, wherein the time information includes a real number part and an exponential part.
Claim 18
Dependent Claim
33 words
The error detecting method for use in the digital data communication processor as set forth in claim 12, wherein the tracing includes tracing the state of a program stored in the program ROM.
Claim 19
Dependent Claim
74 words
A digital data communication controller formed on a semiconductor substrate comprising: sequence control means for storing microprograms that generate sequence control signals to perform various control actions according to specified state and event code; and memory means operatively associated with said sequence control for successively storing state and event information corresponding to the specified state and event code and time information concerning the time spent in each state according to the specified state code.
Claim 20
Dependent Claim
74 words
A digital data communication controller formed on a semiconductor substrate comprising: sequence control means for storing microprograms that generate sequence control signals to perform various control actions according to specified state and event code; and memory means operatively associated with said sequence control for successively storing state and event information corresponding to the specified state and event code and time information concerning the time spent in each state according to the specified state code.
Claim 21
Dependent Claim
59 words
The digital data communication controller as set forth in claim 16, wherein the sequence control means comprises decoding means for decoding the specified state and event code and for generating microprogram memory address signals, and microprogram memory means, wherein the microprogram memory means stores microinstruction codes and executes a routine program according to the specified state and event code.
Claim 22
Dependent Claim
19 words
The digital data communication controller as set forth in claim 17, wherein the memory means is a FIFO memory.
Claim 23
Dependent Claim
24 words
The digital data communication controller as set forth in claim 17, wherein the decoding means and the microprogram memory means are formed of ROM.
Claim 24
Dependent Claim
27 words
The digital data communication controller as set forth in claim 17, wherein at least either of the decoding means and the microprogram memory is formed of RAM.
Claim 25
Dependent Claim
45 words
The digital data communication controller as set forth in claim 17, wherein the state information to be stored in said memory means successively corresponds to current states and the event information to be stored in said memory means corresponds to events which generate state transitions.
Claim 26
Dependent Claim
31 words
The digital data communication controller as set forth in claim 21, wherein the time information to be stored in said memory means includes a real number part and an exponential part.
Claim 27
Dependent Claim
111 words
An error detecting assembly incorporated into digital data communication controller which is formed on a semiconductor substrate and which includes a microprogram ROM, wherein said microprogram ROM forms sequential control signals for executing selected sequence control operations depending on state and event code, said error detecting assembly comprising: a memory circuit for successively storing a contents including state and event information corresponding to the state and event code and time information concerning the time spent by each state; and, a reading means for reading the contents of said memory circuit wherein the contents of said memory circuit is used to reveal the states through which the sequence control operations have passed.
Claim 28
Dependent Claim
111 words
An error detecting assembly incorporated into digital data communication controller which is formed on a semiconductor substrate and which includes a microprogram ROM, wherein said microprogram ROM forms sequential control signals for executing selected sequence control operations depending on state and event code, said error detecting assembly comprising: a memory circuit for successively storing a contents including state and event information corresponding to the state and event code and time information concerning the time spent by each state; and, a reading means for reading the contents of said memory circuit wherein the contents of said memory circuit is used to reveal the states through which the sequence control operations have passed.
Claim 29
Dependent Claim
43 words
The error detecting assembly incorporated into the digital communication controller as set forth in claim 23, wherein said contents of said memory circuit is supplied to tracing means for tracing the state of the sequence control operations executed in said digital communication controller.
Claim 30
Dependent Claim
29 words
The error detecting means incorporated into digital data communication controller as set forth in claim 21, wherein the time information includes a real number part and an exponential part.
Claim 31
Dependent Claim
50 words
The error detecting assembly incorporated into digital data communication controller as set forth in claim 25, wherein the state information to be stored in said memory circuit successively corresponds to current states and the event information to be stored in said memory circuit corresponds to events which generate state transitions.
Claim 32
Dependent Claim
139 words
An error detecting method for use in a digital data communication controller formed on a semiconductor substrate, said error detecting method comprising the steps of: operating a microprogram ROM, wherein said operating forms sequential control operations depending on state and event code, wherein the operating comprises passing through a plurality of states; successively storing information in a memory circuit wherein said information includes state and event information corresponding to the state and event code and time information concerning the time spent by each state depending on the state code; reading the contents of said memory circuit wherein the contents of said memory circuit reveal the states through which the sequence control operations have passed; and, tracing the each state of the sequence control operations executed in said digital data communication controller by using the contents of said memory circuit.
Claim 33
Dependent Claim
139 words
An error detecting method for use in a digital data communication controller formed on a semiconductor substrate, said error detecting method comprising the steps of: operating a microprogram ROM, wherein said operating forms sequential control operations depending on state and event code, wherein the operating comprises passing through a plurality of states; successively storing information in a memory circuit wherein said information includes state and event information corresponding to the state and event code and time information concerning the time spent by each state depending on the state code; reading the contents of said memory circuit wherein the contents of said memory circuit reveal the states through which the sequence control operations have passed; and, tracing the each state of the sequence control operations executed in said digital data communication controller by using the contents of said memory circuit.
Claim 34
Dependent Claim
49 words
The error detecting method for use in the digital data communication controller as set forth in claim 27, wherein the state information to be stored in said memory circuit is present state information and the event information to be stored in said memory circuit is state transition event information.
Claim 35
Dependent Claim
31 words
The error detecting method for use in the digital data communication controller as set forth in claim 28, wherein the time information includes a real number part and an exponential part.
Claim 36
Dependent Claim
33 words
The error detecting method for use in the digital data communication controller as set forth in claim 27, wherein the tracing includes tracing the state of a program stored in the microprogram ROM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |