US5901283A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer
Assignee: Renesas Design Corp
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Filing: 1997-01-28
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Granted: 1999-05-04
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Expires: 2017-01-28
Abstract
Abstract A microcomputer includes a central processing unit for sequentially executing instructions according to a software program. When the CPU decodes a marker, the CPU determines the location of the marker within the software program and produces a marker decoding signal showing that the CPU has decoded the marker. A monitor unit obtains CPU operation information about operation of the CPU in response to the marker decoding signal. The monitor unit provides to a storage unit the CPU operation information and a marker identifier showing that the marker has been decoded.
Inventors
- 👤 Teruaki Kanzaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:18
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
173 words
A microcomputer comprising: a central processing unit (CPU) for sequentially executing instructions in a software program; a monitor unit coupled to said CPU for tracing instructions executed by said CPU and outputting instruction information to a storage unit; a trace flag register coupled to said monitor unit including a trace flag having a first state for enabling said monitor unit to output the instruction information to the storage unit and a second state for preventing said monitor unit from outputting the instruction information to the storage unit; and a detailed trace flag register coupled to said monitor unit including a detailed trace flag having a first state for enabling said monitor unit to output detailed trace information to the storage unit, the detailed trace information including instruction information, address information, and data information of the instructions executed by said CPU and a second state for enabling said monitor unit to output marker information to the storage unit and for preventing said monitor unit from outputting the detailed trace information to the storage unit.
Claim 2
Dependent Claim
173 words
A microcomputer comprising: a central processing unit (CPU) for sequentially executing instructions in a software program; a monitor unit coupled to said CPU for tracing instructions executed by said CPU and outputting instruction information to a storage unit; a trace flag register coupled to said monitor unit including a trace flag having a first state for enabling said monitor unit to output the instruction information to the storage unit and a second state for preventing said monitor unit from outputting the instruction information to the storage unit; and a detailed trace flag register coupled to said monitor unit including a detailed trace flag having a first state for enabling said monitor unit to output detailed trace information to the storage unit, the detailed trace information including instruction information, address information, and data information of the instructions executed by said CPU and a second state for enabling said monitor unit to output marker information to the storage unit and for preventing said monitor unit from outputting the detailed trace information to the storage unit.
Claim 3
Dependent Claim
81 words
The microcomputer according to claim 1 wherein said monitor unit outputs the detailed trace information to the storage unit in response to the first state of the trace flag and the first state of the detailed trace flag and said monitor unit outputs marker information to the storage unit and is prevented from outputting the detailed trace information to the storage unit in response to the first state of the trace flag and the second state of the detailed trace flag.
Claim 4
Dependent Claim
25 words
The microcomputer according to claim 1 wherein the marker information includes an address of a marker instruction and an identifier for identifying the marker instruction.
Claim 5
Dependent Claim
25 words
The microcomputer according to claim 2 wherein the marker information includes an address of a marker instruction and an identifier for identifying the marker instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-03 | 2002-11-02 | 2003-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-03 | 2010-11-02 | 2011-05-04 | $7700.00 | Window Closed / Lapsed |