EP0530816A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microprocessor with cache memory and trace analyzer therefor
Assignee: NEC Corp
•
Filing: 1992-09-03
•
Granted: —
•
Expires: 2012-09-03
Abstract
Abstract A terminal externally indicating whether or not a cache memory included in a microprocessor is made valid is provided in the microprocessor. A trace analyzer responds to a signal on the terminal to change a tracing method of the microprocessor. As a result, debugging of a program to be executed in real time can be done easily.
Inventors
- 👤 Hiroaki C/O Nec Corporation Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:51
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
72 words
A microprocessor with cache memory, comprising: an internal register adapted to be set with a cache memory valid or a cache memory invalid according to a result of execution of instruction or an internal state; a mode detecting mechanism for detecting whether or not said cache memory is valid according to a content of said internal register; and a mode exhibit terminal for externally indicating an output of said mode detecting mechanism.
Claim 2
Dependent Claim
28 words
The microprocessor claimed in claim 1, further comprising a cache valid terminal for externally indicating to said mode detecting mechanism whether said cache memory is valid or invalid.
Claim 3
Dependent Claim
32 words
The microprocessor claimed in claim 1, further comprising a plurality of terminals for externally indicating whether or not an execution start, a branch generation and a branch address can be determined stationarily.
Claim 4
Dependent Claim
31 words
A trace analyzer for use with the microprocessor claimed in claim 1, wherein a trace method of said microprocessor is changed in response to a signal on a mode exhibit terminal.
Claim 5
Dependent Claim
113 words
The trace analyzer claimed in claim 4 for use with the microprocessor claimed in claim 3, further comprising an execution flow obtained by preliminarily analyzing a program stationarily and an interrupt generating mechanism for generating an interrupt for a case of said branch where said branch address can not be determined stationarily, and wherein, when said signal on said mode exhibit terminal indicates that said cache memory is valid, a trace of said microprocessor is performed by dynamically assembling instruction execution sequence on the basis of said execution flow or said interrupt generating mechanism according to an indication whether or not said execution start, branch generation and branch address can be determined stationarily.
Claim 6
Dependent Claim
39 words
The trace analyzer claimed in claim 4 for use with the microprocessor claimed in claim 1, wherein, when said signal on said mode exhibit terminal indicates that said cache memory is valid, a trace of said microprocessor is stopped.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.