US5802272A
Expired / Lapsed
US
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Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-12-19
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Granted: 1998-09-01
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Expires: 2014-12-19
Abstract
Abstract An operation of a processor is traced while fetching instructions from a memory to operate the processor. The tracing involves detecting an unpredictable fetching of instructions on the assumption that a predictable fetching can be reconstructed without any further input. The unpredictable fetching is identified as being due to either computable, conditional, or unanticipated events. Upon detecting the events, process control information, such as the next instruction to be fetched is recorded in a queue, and from the queue the information can be stored in a trace buffer. During reconstruction of the operation, the trace buffer, and the image including the instructions can be examined to analyze the real-time operation of the processor.
Inventors
- 👤 Richard L. Sites
- 👤 Sharon E. Perl
- 👤 G. Michael Uhler
- 👤 David G. Conroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466; G06F2201/00; G06F2201/865
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
83 words
An apparatus for tracing execution flows during an operation of a processor, comprising: a memory storing instructions at addresses; means for fetching instructions from the memory to operate the processor; means, coupled to the means for fetching, for detecting the fetching of the instructions; means, responsive to the detecting of the fetching, for recording information related to only an unpredictable fetching of the instruction; and a trace buffer for storing the information to trace the execution flows while the instructions operate the processor.
Claim 2
Independent Claim
83 words
An apparatus for tracing execution flows during an operation of a processor, comprising: a memory storing instructions at addresses; means for fetching instructions from the memory to operate the processor; means, coupled to the means for fetching, for detecting the fetching of the instructions; means, responsive to the detecting of the fetching, for recording information related to only an unpredictable fetching of the instruction; and a trace buffer for storing the information to trace the execution flows while the instructions operate the processor.
Claim 3
Dependent Claim
110 words
The apparatus as in claim 1 further comprising; means for identifying the unpredictable fetching as computable, conditional, or unanticipated, respectively; and in the case of the unpredictable fetching being identified as computable, conditional, or unanticipated, the means for recording in the trace buffer the information further including, respectively: means for recording in the trace buffer the address of a next instruction to fetch, means for recording in the trace buffer a logical state of the processor to determine the address of the next instructions to fetch, and means for recording in the trace buffer the address of a last instruction fetched and the address of the next instruction to fetch.
Claim 4
Dependent Claim
46 words
The apparatus as in claim 2 further comprising: means for identifying a jump instruction, a call instruction, and a return instruction; means for identifying a conditional branch instruction; and means for identifying a processor interrupt, to identify the unpredictable fetching as computable, conditional, or unanticipated, respectively.
Claim 5
Dependent Claim
115 words
The apparatus as in claim 1 further comprising: a queue storing timing and event information related to when and how the unpredictable fetching occurred, the queue having a plurality of entries, each entry storing the timing and event information for an occurrence of the unpredictable fetching of the instructions; a driver reading the timing and event information stored in the plurality of entries of the queue; a port of the processor connected to the trace buffer, the port communicating the timing and event information read from the queue by the driver to the trace buffer, the port communicating the timing and event information at a rate determined by a clock signal generated by the processor.
Claim 6
Dependent Claim
54 words
The apparatus as in claim 4 further comprising: a shift register connected to the means for identifying the conditional branch instruction, the shift register storing a plurality of the conditions of logical states of the processor as bit values, and a count value representing the number of bit values stored in the shift register.
Claim 7
Dependent Claim
33 words
The apparatus as in claim 5 further comprising: means for storing the bit values and the count value of the shift register in the queue when the count value reaches a predetermined value.
Claim 8
Dependent Claim
29 words
The apparatus as in claim 5 further comprising: means for storing the bit values and the count value of the shift register in the queue upon detecting the interrupt.
Claim 9
Dependent Claim
17 words
The apparatus as in claim 4 wherein the trace buffer is an allocated portion of the memory.
Claim 10
Dependent Claim
80 words
The apparatus as in claim 1 further comprising: a queue storing the timing and event information related to the unpredictable fetching, the queue having a plurality of entries, each entry storing the timing and event information for an occurrence of the unpredictable fetching of the instructions; means for detecting when the queue is full; and means, responsive to a signal which indicates that the queue is full, for communicating the timing and event information of the queue to the memory.
Claim 11
Dependent Claim
58 words
The apparatus as in claim 5 further comprising: means for reading the instructions stored in the memory; and means for reading the timing and event information communicated to the trace buffer; and means for processing the instructions according to the timing and event information to reconstruct the execution flows as they were during the operation of the processor.
Claim 12
Dependent Claim
54 words
The apparatus as in claim 4 further comprising: means for reading the instructions stored in the memory while fetching the instructions from the memory to operate the processor; means for reading the timing and event information communicated to the trace buffer while fetching the instructions to analyze the operation of the processor in real-time.
Claim 13
Dependent Claim
50 words
The apparatus as in claim 1 further comprising: a virtual memory storing the instructions at a plurality of address spaces; means for detecting a context switch of the plurality of address spaces; and means, responsive to the context switch, for recording timing and event information related to the context switch.
Claim 14
Dependent Claim
28 words
The apparatus as in claim 12 wherein the timing and event information related to the context switch is an identifier of one of the plurality of address spaces.
Claim 15
Independent Claim
75 words
A method for tracing an operation of a processor, comprising: storing instructions at addresses of a memory; fetching the instructions from the memory to operate the processor; detecting an unpredictable fetching of the instructions; and in responsive to the unpredictable fetching of the instructions, recording in a temporal order information related to when and how the unpredictable fetching of the instructions occurred in a trace buffer, to trace the execution flows while operating the processor.
Claim 16
Independent Claim
75 words
A method for tracing an operation of a processor, comprising: storing instructions at addresses of a memory; fetching the instructions from the memory to operate the processor; detecting an unpredictable fetching of the instructions; and in responsive to the unpredictable fetching of the instructions, recording in a temporal order information related to when and how the unpredictable fetching of the instructions occurred in a trace buffer, to trace the execution flows while operating the processor.
Claim 17
Dependent Claim
82 words
The method as in claim 14 further comprising: identifying the unpredictable fetching as computable, conditional, or unanticipated, respectively; and in the case of the unpredictable fetching being identified as computable, conditional, and unanticipated, the recording further including, respectively, recording an address of a next instruction to fetch, recording a logical state of the processor to determine the address of the next instructions to fetch, and recording an address of a last instruction fetched and the address of the next instruction to fetch.
Claim 18
Dependent Claim
39 words
The method as in claim 15 further comprising: identifying a jump instruction, a call instruction, and a return instruction; identifying a conditional branch instruction; and identifying an interrupt, while identifying the unpredictable fetching as computable, conditional, or unanticipated, respectively.
Claim 19
Dependent Claim
26 words
The method as in claim 14 further comprising: recording a time of an occurrence of the unpredictable fetching with the information related to the unpredictable fetching.
Claim 20
Dependent Claim
88 words
The method as in claim 14 further comprising: storing the information related to the unpredictable fetching in a queue, the queue having a plurality of entries, each entry storing the information for an occurrence of the unpredictable fetching of the instructions; reading the information stored in the plurality of entries of the queue with a driver; communicating the information read from the queue by the driver to a trace buffer via a port, the port communicating at a rate determined by a clock signal generated by the processor.
Claim 21
Dependent Claim
45 words
The method as in claim 18 further comprising: storing a plurality of conditions of logical states of the processor as bit values in a shift register; and maintaining a count value representing number of bit values stored in the shift register with the bit values.
Claim 22
Dependent Claim
31 words
The method as in claim 19 further comprising: storing the bit values and the count value of the shift register in the queue when the count value reaches a predetermined value.
Claim 23
Dependent Claim
27 words
The method as in claim 19 further comprising: storing the bit values and the count value of the shift register in the queue upon detecting an interrupt.
Claim 24
Dependent Claim
18 words
The method as in claim 18 further comprising: allocating a portion of the memory as the trace buffer.
Claim 25
Dependent Claim
35 words
The method as in claim 18 further comprising: reading the instructions stored in the memory; and reading the information communicated to the trace buffer while reading the instructions to reconstruct the operation of the processor.
Claim 26
Dependent Claim
47 words
The method as in claim 18 further comprising: reading the instructions stored in the memory while fetching the instructions from the memory to operate the processor; reading the information communicated to the trace buffer while fetching the instructions to analyze the operation of the processor in real-time.
Claim 27
Dependent Claim
46 words
The method as in claim 14 further comprising: storing the instructions in a virtual memory having a plurality of address spaces; detecting a context switch of the plurality of address spaces; and in response to detecting the context switch, recording information related to the context switch.
References Cited (Backward Citations)
US5321828A
Cited
US5499355A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |