US5499355A
Expired / Lapsed
US
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Prefetching into a cache to minimize main memory access time and cache size in a computer system
Assignee: Rambus Inc
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Filing: 1994-11-15
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Granted: 1996-03-12
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Expires: 2014-11-15
Abstract
Abstract A cache subsystem for a computer system having a processor and a main memory is described. The cache subsystem includes a prefetch buffer coupled to the processor and the main memory. The prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor. The predicted address is based upon an address for a last memory fetch from the processor. A main cache is coupled to the processor and the main memory. The main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer. The main cache stores a second data fetched from the main memory in accordance with the address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address. The address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
Inventors
- 👤 Karnamadakala Krishnamohan
- 👤 Paul M. Farmwald
- 👤 Frederick A. Ware
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:16
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F2212/00; G06F2212/60; G06F2212/6022; G06F2212/6026
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
175 words
A cache subsystem for a computer system having a processor and a main memory, comprising: (A) a prefetch buffer coupled to the processor and the main memory, wherein the prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor, wherein the predicted address is generated based upon a last memory fetch from the processor; (B) a main cache coupled to the processor and the main memory, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer, wherein the main cache stores a second data fetched from the main memory in accordance with an address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address, wherein the address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
Claim 2
Dependent Claim
175 words
A cache subsystem for a computer system having a processor and a main memory, comprising: (A) a prefetch buffer coupled to the processor and the main memory, wherein the prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor, wherein the predicted address is generated based upon a last memory fetch from the processor; (B) a main cache coupled to the processor and the main memory, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer, wherein the main cache stores a second data fetched from the main memory in accordance with an address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address, wherein the address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
Claim 3
Dependent Claim
28 words
The cache subsystem of claim 1, wherein the predicted address is equal to a next sequential address from the address of the last memory fetch from the processor.
Claim 4
Dependent Claim
22 words
The cache subsystem of claim 1, further comprising a prefetch assist cache that stores the predicted address for the next memory fetch.
Claim 5
Dependent Claim
31 words
The cache subsystem of claim 3, wherein the prefetch buffer generates the predicted address by reading the prefetch assist cache using the address of the last memory fetch from the processor.
Claim 6
Dependent Claim
36 words
The cache subsystem of claim 4, wherein the predicted address is equal to a next sequential address from the address of the last memory fetch if the prefetch assist cache does not contain the predicted address.
Claim 7
Dependent Claim
46 words
The cache subsystem of claim 1, wherein the each of the first and second data prefetched by the prefetch buffer is a main memory data line from the main memory from the predicted address wherein the main memory data line comprises a plurality of data bytes.
Claim 8
Dependent Claim
61 words
The cache subsystem of claim 1, wherein the prefetch buffer comprises: instruction prefetch buffer that generates the predicted address for a next instruction fetch by the processor if the last memory fetch is an instruction fetch; data prefetch buffer that generates the predicted address for a next data fetch by the processor if the last memory fetch is a data fetch.
Claim 9
Dependent Claim
37 words
The cache subsystem of claim 7, further comprising a stride predictor circuit that stores a program counter address and a virtual address corresponding to the program counter address during execution of a load instruction by the processor.
Claim 10
Dependent Claim
36 words
The cache subsystem of claim 8, wherein the data prefetch buffer generates the predicted address for the next data fetch by reading the virtual address corresponding to the program counter address from the stride predictor circuit.
Claim 11
Dependent Claim
188 words
A computer system, comprising: (A) a processor; (B) a main memory; (C) a cache subsystem coupled to the processor and the main memory, wherein the cache subsystem further comprises (i) a prefetch buffer coupled to the processor and the main memory, wherein the prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor, wherein the predicted address is based upon a last memory fetch from the processor; (ii) a main cache coupled to the processor and the main memory, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer, wherein the main cache stores a second data fetched from the main memory in accordance with an address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address, wherein the address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
Claim 12
Dependent Claim
188 words
A computer system, comprising: (A) a processor; (B) a main memory; (C) a cache subsystem coupled to the processor and the main memory, wherein the cache subsystem further comprises (i) a prefetch buffer coupled to the processor and the main memory, wherein the prefetch buffer stores a first data prefetched from the main memory in accordance with a predicted address for a next memory fetch by the processor, wherein the predicted address is based upon a last memory fetch from the processor; (ii) a main cache coupled to the processor and the main memory, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer, wherein the main cache stores a second data fetched from the main memory in accordance with an address for the last memory fetch by the processor only if the address for the last memory fetch is an unpredictable address, wherein the address for the last memory fetch is the unpredictable address if both of the prefetch buffer and the main cache do not contain the address and the second data associated with the address.
Claim 13
Dependent Claim
28 words
The computer system of claim 10, wherein the predicted address is equal to a next sequential address from the address of the last memory fetch from the processor.
Claim 14
Dependent Claim
25 words
The computer system of claim 10, wherein the cache subsystem includes a prefetch assist cache that stores the predicted address for the next memory fetch.
Claim 15
Dependent Claim
31 words
The computer system of claim 12, wherein the cache subsystem generates the predicted address by reading the prefetch assist cache using the address of the last memory fetch from the processor.
Claim 16
Dependent Claim
36 words
The computer system of claim 13, wherein the predicted address is equal to a next sequential address from the address of the last memory fetch if the prefetch assist cache does not contain the predicted address.
Claim 17
Dependent Claim
62 words
The computer system of claim 10, wherein the prefetch buffer further comprises instruction prefetch buffer that generates the predicted address for a next instruction fetch by the processor if the last memory fetch is an instruction fetch; data prefetch buffer that generates the predicted address for a next data fetch by the processor if the last memory fetch is a data fetch.
Claim 18
Dependent Claim
41 words
The computer system of claim 15, wherein the cache subsystem further comprises a stride predictor circuit that stores a program counter address and a virtual address corresponding to the program counter address during execution of a load instruction by the processor.
Claim 19
Dependent Claim
36 words
The computer system of claim 16, wherein the data prefetch buffer generates the predicted address for the next data fetch by reading the virtual address corresponding to the program counter address from the stride predictor circuit.
Claim 20
Dependent Claim
174 words
A memory access method in a cache subsystem coupled to a process and a main memory in a computer system, comprising the steps of: (A) receiving an address for a memory fetch from the processor; (B) determining if the address is an unpredictable address by determining if the address is contained in the cache subsystem, wherein the address is an unpredictable address if the cache subsystem does not contain the address; (C) if the address is an unpredictable address, then fetching a first data from the main memory into a main cache of the cache subsystem in accordance with the unpredictable address, wherein the main cache only stores data fetched by unpredictable addresses; (D) generating a predicted address for a next memory fetch by the processor based upon the unpredictable address and prefetching a second data from the main memory from the predicted address and then storing the second data in a prefetch buffer, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer.
Claim 21
Dependent Claim
174 words
A memory access method in a cache subsystem coupled to a process and a main memory in a computer system, comprising the steps of: (A) receiving an address for a memory fetch from the processor; (B) determining if the address is an unpredictable address by determining if the address is contained in the cache subsystem, wherein the address is an unpredictable address if the cache subsystem does not contain the address; (C) if the address is an unpredictable address, then fetching a first data from the main memory into a main cache of the cache subsystem in accordance with the unpredictable address, wherein the main cache only stores data fetched by unpredictable addresses; (D) generating a predicted address for a next memory fetch by the processor based upon the unpredictable address and prefetching a second data from the main memory from the predicted address and then storing the second data in a prefetch buffer, wherein the main cache is not coupled to the prefetch buffer and does not receive data from the prefetch buffer.
Claim 22
Dependent Claim
28 words
The method of claim 18, wherein the step (D) further comprises the step of generating the predicted address equal to a next sequential address from the unpredictable address.
Claim 23
Dependent Claim
28 words
The method of claim 18, wherein the step (D) further comprises the step of generating the predicted address by reading a prefetch assist cache using the unpredictable address.
Claim 24
Dependent Claim
35 words
The method of claim 20, further comprising the step of generating the predicted address equal to a next sequential address of the unpredictable address if the prefetch assist cache does not contain the predicted address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |