EP0449540A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processing system and method with small fully-associative cache and prefetch buffers
Assignee: Compaq Computer Corp
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Filing: 1991-03-25
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Granted: —
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Expires: 2011-03-25
Abstract
Abstract A memory system (10) utilizes miss caching by incorporating a small fully-associative miss cache (42) between a cache (18 or 20) and second-level cache (26). Misses in the cache (18 or 20) that hit in the miss cache have only a one cycle miss penalty, as opposed to a many cycle miss penalty without the miss cache (42). Victim caching is an improvement to miss caching that loads a small, fully associative cache (52) with the victim of a miss and not the requested line. Small victim caches (52) of 1 to 4 entries are even more effective at removing conflict misses than miss caching. Stream buffers (62) prefetch cache lines starting at a cache miss address. The prefetched data is placed in the buffer (62) and not in the cache (18 or 20). Stream buffers (62) are useful in removing capacity and compulsory cache misses, as well as some instruction cache misses. Stream buffers (62) are more effective than previously investigated prefetch techniques when the next slower level in the memory hierarchy is pipelined. An extension to the basic stream buffer, called multi-way stream buffers (62), is useful for prefetching along multiple intertwined data reference streams.
Inventors
- 👤 Norman P. Jouppi
- 👤 Alan Eustace
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:17
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; G06F2212/00; G06F2212/60; G06F2212/6022
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
116 words
A memory system (10), which comprises a first cache memory (18, 20), a second memory (26), a stream buffer (62) connected between said first cache memory and said second memory, and means (16), connected to said first cache memory, said second memory and said stream buffer for addressing information and for supplying information to said first cache memory and to said stream buffer when a miss occurs in said first cache memory for addressed information, said means for addressing information and for supplying information including means for supplying missed information in said first cache memory and for supplying information in at least one address successive to an address for the missed information to said stream buffer.
Claim 2
Dependent Claim
17 words
The memory system of Claim 1 in which said first cache memory comprises an instruction cache (18).
Claim 3
Dependent Claim
18 words
The memory system of Claim 2 in which said first cache memory additionally comprises a data cache (20).
Claim 4
Dependent Claim
38 words
The memory system of any one of Claims 1 to 3 in which said means for addressing information and for supplying information includes means for supplying information addresses simultaneously to said first cache memory and said stream buffer.
Claim 5
Dependent Claim
37 words
The memory system of any one of Claims 1 to 4 in which said means for addressing information and for supplying information includes means for supplying corresponding information to said first cache memory and said stream buffer.
Claim 6
Dependent Claim
77 words
The memory system of any one of Claims 1 to 5 in which said system includes an additional plurality of stream buffers connected between said first cache memory and said second memory, and said means for addressing information and for supplying information includes means for supplying missed data in said first cache memory and for supplying data in at least one address successive to an address for the missed data to said additional plurality of stream buffers.
Claim 7
Dependent Claim
38 words
The memory system of any one of Claims 1 to 6 in which said means for addressing information and for supplying information includes means for supplying missed information from one of said stream buffer and said second memory.
Claim 8
Dependent Claim
22 words
The memory system of any one of Claims 1 to 7 in which said first cache memory is a direct-mapped cache memory.
Claim 9
Dependent Claim
90 words
A memory system (10), which comprises a first cache memory (18, 20), a second memory (26), and associative miss cache (42, 52), having a smaller memory capacity than said first cache memory and connected between said first cache memory and said second memory, and means (16), connected to said first cache memory, said second memory and said associative miss cache for addressing information and for supplying information to said first cache memory and to said associative miss cache when a miss occurs in said first cache memory for addressed information.
Claim 10
Dependent Claim
16 words
The memory system of Claim 9 in which said first cache memory comprises an instruction cache.
Claim 11
Dependent Claim
22 words
The memory system of either one of Claims 9 and 10 in which said first cache memory additionally comprises a data cache.
Claim 12
Dependent Claim
39 words
The memory system of any one of Claims 9 to 11 in which said means for addressing information and for supplying information includes means for supplying information addresses simultaneously to said first cache memory and said associative miss cache.
Claim 13
Dependent Claim
38 words
The memory system of any one of Claims 9 to 12 in which said means for addressing information and for supplying information includes means for supplying corresponding information to said first cache memory and said associative miss cache.
Claim 14
Dependent Claim
51 words
The memory system of Claim 10 or any one of Claims 11 to 13 as appended to Claim 10 in which said means for addressing information and for supplying information includes means for supplying information from one of said associative miss cache and said second memory to said first cache memory.
Claim 15
Dependent Claim
61 words
The memory system of Claim 14 in which said first cache memory is a direct-mapped cache memory and in which said means for addressing information and for supplying information includes means for supplying information from the first, direct-mapped cache memory displaced by the information from said one of said associative miss cache and said second memory to said associative miss cache.
Claim 16
Dependent Claim
41 words
The memory system of Claim 15 in which said means for addressing information and for supplying information includes means for supplying correct information to said first, direct-mapped cache memory from said associative miss cache in the event of a parity error.
Claim 17
Dependent Claim
84 words
The memory system of either one of Claims 15 and 16 in which the information comprises data additionally including an instruction portion, said system additionally includes a stream buffer connected between said first, direct-mapped cache memory and said second memory, and said means for addressing information and for supplying information includes means for supplying a missed instruction in said first, direct-mapped cache memory and for supplying information in at least one address successive to an address for the missed instruction to said stream buffer.
Claim 18
Dependent Claim
74 words
The memory system of Claim 17 in which said system includes an additional plurality of stream buffers connected between said first, direct-mapped cache memory and said second memory, and said means for addressing information and for supplying information includes means for supplying missed data in said first, direct-mapped cache memory and for supplying data in at least one address successive to an address for the missed data to said additional plurality of stream buffers.
Claim 19
Dependent Claim
52 words
A memory accessing method, which comprises addressing a first cache memory, determining if a miss occurs in the first cache memory in response to the addressing, and supplying information from a second memory to the first cache memory and to a miss cache when a miss occurs in the first cache memory.
Claim 20
Dependent Claim
24 words
The memory accessing method of Claim 19 in which information addresses are supplied simultaneously to the first cache memory and to the miss cache.
Claim 21
Dependent Claim
41 words
The memory accessing method of either one of Claims 19 and 20 in which corresponding information is supplied from the second memory to the first cache memory and to the miss cache when a miss occurs in the first cache memory.
Claim 22
Dependent Claim
82 words
The memory accessing method of any one of Claims 19 to 21 additionally comprising addressing the miss cache if a miss occurs in the first cache memory, and supplying information from the miss cache in response to the addressing in the absence of a miss in the miss cache, and in which information is supplied from the second memory to the first cache memory and to the miss cache when a miss occurs in the first memory and in the miss cache.
Claim 23
Dependent Claim
39 words
The memory accessing method of any one of Claims 19 to 22 in which information from the first cache memory displaced by information from one of the miss cache and the second memory is supplied to the miss cache.
Claim 24
Dependent Claim
35 words
The memory accessing method of Claim 23 including the steps of detecting a parity error and supplying corresponding information to the first cache memory from the miss cache in the event of a parity error.
Claim 25
Dependent Claim
65 words
The memory accessing method of either one of Claims 23 and 24 in which the information comprises data which additionally includes an instruction portion, and the method includes the steps of supplying a missed instruction in the first cache memory to the first cache memory and supplying information in at least one address successive to an address for the missed instruction to a stream buffer.
Claim 26
Dependent Claim
49 words
The memory accessing method of Claim 25 additionally including the step of supplying missed data in the first cache memory to the first cache memory and supplying the data in at least one address successive to an address for the missed data to an additional plurality of stream buffers.
Claim 27
Dependent Claim
53 words
A memory accessing method, which comprises addressing a first cache memory, determining if a miss occurs in the first cache memory in response to the addr essing, and supplying information from a second memory to the first cache memory and to a stream buffer when a miss occurs in the first cache memory.
Claim 28
Dependent Claim
24 words
The memory accessing method of Claim 27 in which information addresses are supplied simultaneously to the first cache memory and to the stream buffer.
Claim 29
Dependent Claim
41 words
The memory accessing method of either one of Claims 27 and 28 in which corresponding information is supplied from the second memory to the first cache memory and to the stream buffer when a miss occurs in the first cache memory.
Claim 30
Dependent Claim
52 words
The memory accessing method of Claim 29 in which the method includes the steps of supplying missed information in the first cache memory to the first cache memory and supplying the missed information and information in at least one address successive to an address for the missed information to the stream buffer.
Claim 31
Dependent Claim
15 words
The memory accessing method of Claim 30 in which the missed information comprises an instruction.
Claim 32
Dependent Claim
57 words
The memory accessing method of Claim 31 additionally including the step of supplying missed data in the first cache memory to the first cache memory and supplying the missed data in the first cache memory and data in at least one address successive to an address for the missed data to an additional plurality of stream buffers.
Claim 33
Dependent Claim
78 words
The memory accessing method of Claim 27 additionally comprising addressing the stream buffer if a miss occurs in the first cache memory, and supplying information from the stream buffer in response to the addressing in the absence of a miss in the stream buffer, and in which information is supplied from the second memory to the first cache memory and to the stream buffer when a miss occurs in the first cache memory and in the stream buffer.
References Cited (Backward Citations)
No citation records indexed.
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