EP0457403A2
Expired / Lapsed
EP
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Multilevel instruction cache, method for using said cache, method for compiling instructions for said cache and micro computer system using such a cache
Assignee: Koninklijke Philips NV
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Filing: 1991-05-10
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Granted: —
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Expires: 2011-05-10
Abstract
Abstract A cache memory for use between a processing unit and a main memory includes a prefetch buffer, a use buffer, and a head buffer. The prefetched buffer is a FIFO or LRU register which prefetches instructions from contiguous memory locations after the address specified by the program counter. The head buffer is a FIFO or LRU register which is utilized to store instructions from the tops of the program blocks which are accessed from main memory following recent cache misses. The use buffer is a relatively large, inexpensive buffer, preferably a directly mapped buffer, which stores recent hits from the prefetched buffer as well as selected instructions from main memory following cache misses.
Inventors
- 👤 Chi-Hung Chi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897; G06F12/0862; G06F12/0888; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/381; G06F9/3814; G06F9/3824; G06F9/383; G06F2212/00; G06F2212/60; G06F2212/6022; G06F2212/6028
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
247 words
A cache memory system for implementing the transfer of instruction codes from a main memory to a processing unit, said processing unit including a program counter the contents of which specify an address in the main memory which contains a next instruction code to be executed by said processing unit, comprising: prefetch buffer means connected to prefetch and store instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter; a head buffer; a use buffer; and instruction transfer control means responsive to the contents of the program counter, the prefetch buffer means, the head buffer, and the use buffer, which function so that: a) if an instruction code specified by the program counter is in the prefetch buffer, said code is transmitted to the processing unit and is also stored in use buffer, b) if the instruction code specified by the program counter is in the head buffer or the use buffer, said code is transmitted to the processing unit; or c) if the instruction code specified by the program counter is not in any of the prefetch buffer means, the head buffer, or the use buffer, said code is fetched from the main memory, transmitted to the processing unit and also 1) stored in the head buffer if the contents of the program counter satisfy a predetermined test or 2) stored in the use buffer if the contents of the program counter do not meet the predetermined test.
Claim 2
Dependent Claim
35 words
The system of Claim 1 where in theinstruction transfer control means further function to remove the code specified by the program counter from the prefetch buffer after said code is stored in the use buffer.
Claim 3
Dependent Claim
28 words
The system of Claim 1 or 2 wherein the instruction transfer control means are responsive to an actual memory address specified by the contents of the program counter.
Claim 4
Dependent Claim
39 words
The system of Claim 1 or 2 wherein the predetermined test is met if the memory address specified by the contents of the program counter is non-sequential with the address of the instruction last executed by the processing unit.
Claim 5
Dependent Claim
51 words
The system of Claim 4 wherein the predetermined test is met if the memory address specified by the contents of the program counter is absolutely displaced from the address of the instruction last executed by the processing unit by an amount which is greater than the size of the use buffer.
Claim 6
Dependent Claim
51 words
The system of Claim 4 wherein the predetermined test is met if the memory address specified by the contents of the program counter is negatively displaced from the address of the instruction last executed by the processing unit by an amount which is greater than the size of the use buffer.
Claim 7
Dependent Claim
23 words
The system of Claim 1 or 2 wherein the prefetch buffer means continuously prefetches instruction codes from sequential addresses in the main memory.
Claim 8
Dependent Claim
56 words
The system of Claim 1 or 2 further comprising prefetch control means connected to the prefetch buffer means, the head buffer and the use buffer which inhibit prefetching of instruction codes from main memory addresses if a requested instruction code is already in any of the prefetch buffer means, the head buffer or the use buffer.
Claim 9
Dependent Claim
18 words
The system of Claim 1 or 2 wherein the use buffer is organized as a direct-mapped cache buffer.
Claim 10
Dependent Claim
18 words
The system of Claim 1 or 2 wherein the use buffer is organized as a associative cache buffer.
Claim 11
Dependent Claim
22 words
The system of Claim 1 or 2 wherein the use buffer is larger than the prefetch buffer and than the head buffer.
Claim 12
Dependent Claim
36 words
The system of Claim 1 or 2 further comprising cache freezing means which controllably inhibit data transfer into the use buffer and the head buffer in response to predefined instruction codes processed by the processing unit.
Claim 13
Dependent Claim
79 words
The system of Claim 12 in combination with instruction compiler means which generate instruction code loops as: first a first block of sequential instructions which specify a first iteration of a loop, then a freeze instruction code which inhibits transfer into the use buffer and the head buffer, then a second block of instructions which implement further iterations of the loop, and then an unfreeze instruction code which permits data transfer into the use buffer and the head buffer.
Claim 14
Dependent Claim
19 words
A microprocessor integrated circuit which comprises the processing unit and the cache system of Claim 1 or Claim 2.
Claim 15
Independent Claim
88 words
A method for compiling computer instruction codes which execute a program loop comprising the steps of: Generating a first block of sequential instruction codes which execute a first iteration of the loop; Generating a next sequential freeze instruction code which inhibits transfer of data into at least parts of a cache memory; Generating a next sequential second block of sequential instruction codes which execute further iterations of the loop; and Generating a next sequential unfreeze instruction which enables transfer of data into said parts of said cache memory.
Claim 16
Dependent Claim
20 words
The method of Claim 15 wherein said parts of said cache memory include a head buffer and a use buffer.
Claim 17
Independent Claim
228 words
A method for operating a computer for implementing the transfer of instruction codes from a main memory to a processing unit, said processing unit including a program counter the contents of which specify an address in the main memory which contains a next instruction code to be executed by said processing unit, comprising: providing a cache with a prefetch buffer, a head buffer and a use buffer; prefetching and storing in the prefetch buffer, instruction codes from addresses in the main memory which sequentially follow the addresses contained in the program counter; if an instruction code specified by the program counter is in the prefetch buffer, transmitting said code to the processing unit and also storing said code in the use buffer; if the instruction code specified by the program counter is in the head buffer or the use buffer, transmitting said code to the processing unit; if the instruction code specified by the program counter is not in any of the prefetch buffer, the head buffer, and the use buffer, fetching said code from the main memory, transmitting said code to the processing unit and also 1) storing said code in the head buffer if the contents of the program counter satisfy a predetermined test or 2) storing said code in the use buffer if the contents of the program counter do not meet the predetermined test.
References Cited (Backward Citations)
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