High-speed integrated circuit testing with JTAG

Claim 2

An integrated circuit having input/output ports and comprising a programmable digital processor connected to a program memory having an address space; and further comprising means for performing boundary-scan testing on the input/output ports of said integrated circuit, wherein said means comprises a finite state machine controller connected to an instruction register that is connected to an instruction decoder, a serial test input port, and a serial test output port coupled to said instruction register; wherein said integrated circuit further comprises: a test data register (TDR) connected to said finite state machine controller and said instruction decoder, and having n-bit locations for serially receiving a test program through said serial test input port, and for transferring said test program in parallel n-bit words into said program memory via said digital processor; and a test control register (JCON) connected to said finite state machine and said instruction decoder for initiating downloading and execution of said test program in order to produce test results; and wherein the test results of said test program are transferred via said programmable digital processor into said test data register for serial transfer through said serial test output port.

Claim 3

The integrated circuit of claim 1 wherein said program memory is a dual-port memory having a first port that is accessed by a data bus, and a second port that is accessed by a program instruction bus.

Claim 4

The integrated circuit of claim 1 wherein said test control register includes a control bit for clocking said programmable digital processor from a system clock signal supplied from a source external to said integrated circuit in lieu of a clock supplied from said means for performing boundary scan testing.

Claim 5

The integrated circuit of claim 1 wherein said test control register includes a control bit for clocking said digital processor from a signal supplied from a test clock external to said integrated circuit in lieu of a clock supplied from said means for performing boundary scan testing.

Claim 6

The integrated circuit of claim 1 wherein said test control register includes a control bit for resetting the programmable digital processor to an initial state.

Claim 7

The integrated circuit of claim 1 further comprising a read only memory, and wherein said test control register includes a control bit for mapping said read only memory into the address space of said program memory, wherein said read only memory controls downloading said test program into said program memory.

Claim 8

The integrated circuit of claim 1 wherein said instruction register includes instructions for: (1) selecting said test control register for a serial write operation; (2) selecting said test control register for a serial read operation; (3) selecting said test data register for a serial write operation; and (4) selecting said test data register for a serial read operation.

Claim 9

The integrated circuit of claim 1 wherein said test control register includes a control bit for enabling block downloading of said test program into said test data register, wherein said test program is received as a continuous sequence of data words after receiving an initial sequence of a given bit pattern.

Claim 10

The integrated circuit of claim 8 wherein said given bit pattern that is sent is a final "1" preceded by (n-1) zeros.

Claim 11

The integrated circuit of claim 1 further comprising: a first status flag means (JINT) connected to said programmable digital processor that is set when said means for performing boundary-scan testing writes a word, and is reset when said programmable digital processor reads a word; and a second status flag means (PINT) connected to said programmable digital processor that is set when said means for performing boundary-scan testing reads a word, and is reset when said programmable digital processor writes a word.

Claim 12

The integrated circuit of claim 10 wherein said first status flag means (JINT) and said second status flag means (PINT) are also connected to said instruction register.

Claim 13

The integrated circuit of claim 10 wherein said first status flag means (JINT) and said second status flag means (PINT) are implemented by means of register bits in said test control register (JCON).

Claim 14

An electronic system comprising a multiplicity of integrated circuits that implement a boundary-scan test according to a Joint Test Action Group (JTAG) boundary-scan test standard, wherein a given integrated circuit comprises a programmable digital processor connected to a program memory having an address space; and wherein said given integrated circuit further comprises: a test data register (TDR) controlled by a JTAG Test Access Port (TAP) controller and a JTAG instruction decoder, and having n-bit locations for serially receiving a test program through a Test Data Input (TDI) serial test input port, and for transferring said test program in parallel n-bit words into said program memory via said programmable digital processor; and a test control register (JCON) controlled by said TAP controller and said JTAG instruction decoder for initiating downloading and execution of said test program in order to produce test results; and wherein the test results of said test program are transferred via said programmable digital processor into said test data register for serial transfer through a Test Data Output (TDO) serial test output port.

Claim 15

An electronic system comprising a multiplicity of integrated circuits that implement a boundary-scan test according to a Joint Test Action Group (JTAG) boundary-scan test standard, wherein a given integrated circuit comprises a programmable digital processor connected to a program memory having an address space; and wherein said given integrated circuit further comprises: a test data register (TDR) controlled by a JTAG Test Access Port (TAP) controller and a JTAG instruction decoder, and having n-bit locations for serially receiving a test program through a Test Data Input (TDI) serial test input port, and for transferring said test program in parallel n-bit words into said program memory via said programmable digital processor; and a test control register (JCON) controlled by said TAP controller and said JTAG instruction decoder for initiating downloading and execution of said test program in order to produce test results; and wherein the test results of said test program are transferred via said programmable digital processor into said test data register for serial transfer through a Test Data Output (TDO) serial test output port.

Claim 16

The system of claim 13 wherein said program memory is a dual-port memory having a first port that is accessed by a data bus, and a second port that is accessed by a program instruction bus.

Claim 17

The system of claim 13 wherein said test control register includes a control bit for clocking said programmable digital processor from a signal supplied from a source external to said given integrated circuit in lieu of a clock supplied from said given integrated circuit.

Claim 18

The system of claim 13 wherein said test control register includes a control bit (JRESET) for resetting the programmable digital processor and beginning test program execution at a given memory location.

Claim 19

The system of claim 13 further comprising a read only memory, and wherein said test control register includes a control bit for mapping said read only memory into the address space of said program memory, wherein said read only memory controls the downloading of said test program into said program memory.

Claim 20

The system of claim 13 wherein said instruction register includes instructions for: (1) selecting said test control register for a serial write operation; (2) selecting said test control register for a serial read operation; (3) selecting said test data register for a serial write operation; and (4) selecting said test data register for a serial read operation.

Claim 21

The system of claim 13 wherein said test control register includes a control bit for enabling block downloading of said test program into said test data register, wherein said test program is sent as a continuous sequence of data words after an initial sequence of a given bit pattern.

Claim 22

The system of claim 13 wherein said given bit pattern that is sent is a final "1" preceded by (n-1) zeros.

Claim 23

An integrated circuit comprising a programmable digital processor connected to a program memory; and further comprising a finite state machine controller connected to an instruction register that is connected to an instruction decoder, a serial test input port and a serial test output port coupled to said instruction register; wherein said integrated circuit further comprises: a test data register (TDR) connected to said finite state machine controller and said instruction decoder, and having n-bit locations for serially receiving a test program through said serial test input port, and for transferring said test program in parallel n-bit words into said program memory; and a test control register (JCON) controlled by said finite state machine controller and said instruction decoder for initiating downloading and execution of said test program in order to produce test results; and wherein said programmable digital processor uploads the test results of said test program into said test data register for serial transfer through said serial test output port, and further comprising means for enabling block downloading of said test program into said test data register, wherein said test program is received as a continuous sequence of data words after receiving an initial sequence of a given bit pattern, and wherein said given bit pattern that is received is a final "1" preceded by a series of all zeros.

Claim 24

An integrated circuit comprising a programmable digital processor connected to a program memory; and further comprising a finite state machine controller connected to an instruction register that is connected to an instruction decoder, a serial test input port and a serial test output port coupled to said instruction register; wherein said integrated circuit further comprises: a test data register (TDR) connected to said finite state machine controller and said instruction decoder, and having n-bit locations for serially receiving a test program through said serial test input port, and for transferring said test program in parallel n-bit words into said program memory; and a test control register (JCON) controlled by said finite state machine controller and said instruction decoder for initiating downloading and execution of said test program in order to produce test results; and wherein said programmable digital processor uploads the test results of said test program into said test data register for serial transfer through said serial test output port, and further comprising means for enabling block downloading of said test program into said test data register, wherein said test program is received as a continuous sequence of data words after receiving an initial sequence of a given bit pattern, and wherein said given bit pattern that is received is a final "1" preceded by a series of all zeros.

Claim 25

The integrated circuit of claim 21 wherein said test program is transferred directly from said test data register into said program memory.

Claim 26

The integrated circuit of claim 21 wherein said test program is transferred from the test data register into said program memory via said programmable digital processor.