EP0511752A1
Expired / Lapsed
EP
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High-speed integrated circuit testing with jtag
Assignee: AT&T Inc
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Filing: 1992-04-14
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Granted: —
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Expires: 2012-04-14
Abstract
Abstract The use of the JTAG port provides for boundary scan testing of integrated circuits, thereby allowing for the testing of IC's after they have been mounted into a circuit board. However, the conventional JTAG scheme is limited as to speed, since both the input and output vectors must be serially shifted in and out of I/O buffers along the chip boundaries. The present invention speeds the testing of high-speed core logic circuitry by transferring the test program to a special test data register (TDR 11), which downloads the program to the logic circuitry under test, and uploads the results. This allows the core logic to perform the test at its normal operating speed, while still retaining compatibility with the JTAG standard for other tests.
Inventors
- 👤 Alan Joel Greenberger
- 👤 Homayoon Sam
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 20:28
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/267
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
164 words
An integrated circuit comprising a programmable digital processor (21,23,24) and a program memory (22); and further comprising means for performing boundary-scan testing on the input/output ports of said integrated circuit, wherein said means comprises a finite state machine controller (302), an instruction register (303), a serial test input port (TDI), and a serial test output port (TDO), Characterized in that said integrated circuit further comprises: a test data register (TDR) (11) controlled by said finite state machine and said instruction decoder, and having n-bit locations for serially receiving a test program through said serial test input port, and for transferring said test program in parallel n-bit words into said program memory; and a test control register (JCON) (10) controlled by said finite state machine and said instruction decoder for initiating the downloading and execution of said test program; and wherein said digital processor uploads the results of said test program into said test data register for serial transfer through said serial test output port.
Claim 2
Dependent Claim
49 words
An integrated circuit as claimed in claim 1 wherein said test control register includes a control bit for clocking said digital processor from a signal supplied from a test clock external to said integrated circuit in lieu of a clock supplied from said means for performing boundary scan testing.
Claim 3
Dependent Claim
28 words
An integrated circuit as claimed in claim 1 wherein said test control register includes a control bit for resetting the programmable digital processor core to an initial state.
Claim 4
Dependent Claim
53 words
An integrated circuit as claimed in claim 1 wherein said test control register includes a control bit for enabling block downloading of said test program into said test data register, wherein said test program is received as a continuous sequence of data words after receiving an initial sequence of a given bit pattern.
Claim 5
Dependent Claim
146 words
An electronic system comprising a multiplicity of integrated circuits that implement the JTAG boundary-scan test standard, wherein a given integrated circuit comprises a programmable digital processor (21,23,24) and a program memory (22); Characterized in that said given integrated circuit further comprises: a test data register (TDR) (11) controlled by the JTAG TAP controller (302) and the JTAG instruction decoder (304), and having n-bit locations for serially receiving a test program through the TDI serial test input port, and for transferring said test program in parallel n-bit words into said program memory; and a test control register (JCON) (10) controlled by said TAP controller (302) and said instruction decoder(304) for initiating the downloading and execution of said test program; and wherein said digital processor uploads the results of said test program into said test data register (11) for serial transfer through the TDO serial test output port.
Claim 6
Dependent Claim
48 words
An integrated circuit as claimed in claim 1 or a system as claimed in claim 5 wherein said program memory is a dual-port memory (22) having a first port that is accessed by a data bus, and a second port that is accessed by a program instruction bus.
Claim 7
Dependent Claim
56 words
An integrated circuit as claimed in claim 1 or a system as claimed in claim 5 wherein said test control register includes a control bit for clocking said digital processor from a signal supplied from a source external to said integrated circuit in lieu of a clock supplied from said means for performing boundary scan testing.
Claim 8
Dependent Claim
27 words
A system as claimed in claim 5 wherein said test control register includes a control bit for resetting the programmable digital processor core to a known state.
Claim 9
Dependent Claim
57 words
An integrated circuit as claimed in claim 1 or a system as claimed in claim 5 wherein said test control register includes a control bit for mapping a read only memory (20) into the address space of said program memory (22), wherein said read only memory controls the downloading of said test program into said program memory.
Claim 10
Dependent Claim
69 words
An integrated circuit as claimed in claim 1 or a system as claimed in claim 5 wherein said instruction register includes the instructions for: (1) selecting said test control register for a serial write operation; (2) selecting said test control register for a serial read operation; (3) selecting said test data register for a serial write operation; and (4) selecting said test data register for a serial read operation.
Claim 11
Dependent Claim
51 words
A system as claimed in claim 5 wherein said test control register includes a control bit for enabling block downloading of said test program into said test data register, wherein said test program is sent as a continuous sequence of data words after an initial sequence of a given bit pattern.
Claim 12
Dependent Claim
189 words
An integrated circuit comprising a programmable digital processor (21,23,24) and a program memory (22); and further comprising a finite state machine controller (302), an instruction register (303), a serial test input port (TDI), and a serial test output port (TDO), Characterized in that said integrated circuit further comprises: a test data register (TDR) (11) controlled by said finite state machine and said instruction decoder, and having n-bit locations for serially receiving a test program through said serial test input port (TDI), and for transferring said test prograin in parallel n-bit words into said program memory (22); and a test control register (JCON) (10) controlled by said finite state machine and said instruction decoder for initiating the downloading and execution of said test program; and wherein said digital processor uploads the results of said test program into said data register (11) for serial transfer through said serial test output port, and further comprising means for enabling block downloading of said test program into said test data register, wherein said test program is received as a continuous sequence of data words after receiving an initial sequence of a given bit pattern.
Claim 13
Dependent Claim
34 words
An integrated circuit as claimed in claim 4 or 12, or a system as claimed in claim 11 wherein said given bit pattern that is sent is a final "1" preceded by (n-1) zeros.
References Cited (Backward Citations)
FR2589264A1
Cited
FR2643992A1
Cited
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