EP0762276A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Data processor with built-in emulation circuit
Assignee: Motorola Solutions Inc
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Filing: 1996-08-22
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Granted: —
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Expires: 2016-08-22
Abstract
Abstract A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
Inventors
- 👤 Joseph C. Circello
- 👤 Klaus R. Riedel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 15:40
CPC Classifications
G; G06; G06F; G06F17/00; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648; G06F9/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
145 words
A data processor (5), comprising: a central processing unit (2) for executing a data processing function, the central processing unit providing an internal processor status signal; bus means for communicating a plurality of information values; and a debug circuit (10), wherein the debug circuit comprises: a control circuit (60) for providing an output control signal; a storage buffer (70) coupled to the bus means for receiving the plurality of information values, the storage buffer providing each of the plurality of information values; and an output circuit coupled (80) to the storage buffer for receiving each of the plurality of information values and coupled to the central processing unit for receiving the internal processor status signal, the output circuit selectively providing the internal processor status signal externally via a status signal and the output circuit selectively providing a debug data value externally via a data signal.
Claim 2
Dependent Claim
27 words
The data processor of claim 1 wherein the status signal and the debug data value indicate a plurality of internal information values to an external development system.
Claim 3
Dependent Claim
16 words
The data processor of claim 1 wherein the debug data value indicates an operand data value.
Claim 4
Dependent Claim
32 words
The data processor of claim 1 further comprising a control status register (40) for storing a configuration value, the control status register coupled to the control circuit for providing the configuration value.
Claim 5
Dependent Claim
30 words
The data processor of claim 1 wherein the configuration value enables the control circuit to configure the storage buffer and the output circuit to perform a real time trace function.
Claim 6
Dependent Claim
26 words
The data processor of claim 1 wherein the data processing function executed by the central processing unit modifies a program flow of the central processing unit.
Claim 7
Dependent Claim
36 words
The data processor of claim 6 wherein the central processing unit provides a target address value to the bus means when executing the data processing function which modifies the program flow of the central processing unit.
Claim 8
Independent Claim
212 words
A method for executing a trace function in a data processor (5), comprising the steps of: initiating execution of a data processing instruction in a central processing unit (2); providing a plurality of internal processor status signals from the central processing unit to a control circuit; communicating a plurality of information values in response to execution of the data processing instruction from the central processing unit via a bus; generating a storage buffer control signal to control operation of a storage buffer (70) during execution of the data processing instruction; sequentially providing each of the plurality of information values to the storage buffer when the storage buffer control signal is asserted; sequentially providing each of a stored plurality of information values from the storage buffer to an output circuit (80); sequentially providing the plurality of internal processor status signals to the output circuit; providing each of the stored plurality of information values via a debug data signal; and concurrently providing a corresponding one of the plurality of internal processor status signals via a status signal, concurrently providing a corresponding one of the plurality of internal processor status signals via a status signal, wherein each of the plurality of internal processor status signals corresponds to one of the stored plurality of information values.
Claim 9
Dependent Claim
73 words
The method of claim 8 further comprising the steps of: providing each of the stored plurality of information values to an external development system via (7) a debug data signal; and concurrently providing a corresponding one of the plurality of internal processor status signals to the external development system via a status signal, wherein each of the plurality of internal processor status signals corresponds to one of the stored plurality of information values.
Claim 10
Dependent Claim
34 words
The method of claim 8 further comprising the step of: storing a configuration value in a control status register (40), the control status register coupled to the control circuit for providing the configuration value.
References Cited (Backward Citations)
GB2200482A
Cited
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