US5930833A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logical cache memory storing logical and physical address information for resolving synonym problems
Assignee: Hitachi Ltd
•
Filing: 1997-08-21
•
Granted: 1999-07-27
•
Expires: 2017-08-21
Abstract
Abstract Physical page information PA(a) corresponding to logical page information VA(a) as a cache tag address is retained in a logical cache memory 10 and in the event of a cache miss when a shared area is accessed, the physical page information PA (a) retained in the cache memory is compared with physical page information PA (b) resulting from the translation of a search address by TLB. When the result of the comparison is proved to be conformity, the cache entry is processes as a cache hit, so that the problem of a synonym arising from a case where the same physical address is assigned to different logical addresses is solved in such a manner that the number of times access is provided to TLB is halved as compared with the conventional arrangement.
Inventors
- 👤 Shinichi Yoshioka
- 👤 Shumpei Kawasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063; G06F2212/00; G06F2212/65; G06F2212/652; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
149 words
A data processor comprising: a logical cache memory containing a plurality of cache entries, each containing logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; wherein each cache entry of the logical cache memory also contains physical address information corresponding to the logical address information in that cache entry; wherein when the cache entry selected by the search information from the logical cache memory does not correspond to a desired logical address, the control unit compares each of the physical address information contained in the logical cache memory with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 2
Dependent Claim
149 words
A data processor comprising: a logical cache memory containing a plurality of cache entries, each containing logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; wherein each cache entry of the logical cache memory also contains physical address information corresponding to the logical address information in that cache entry; wherein when the cache entry selected by the search information from the logical cache memory does not correspond to a desired logical address, the control unit compares each of the physical address information contained in the logical cache memory with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 3
Dependent Claim
25 words
A data processor as claimed in claim 1, wherein the desired logical address shares a physical address space with one or more other logical addresses.
Claim 4
Dependent Claim
173 words
A data processor comprising: a logical cache memory containing logical address information as search information, a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer, the logical cache memory also containing physical address information corresponding to the logical address information in a cache entry, wherein the physical address contained in the cache entry thus selected is utilized for the generation of a physical address for write processing when the cache entry selected by the search information corresponds to a desired logical address, wherein when a cache entry selected by the search information from the logical cache memory does not correspond to the desired logical address, each of the physical address information contained in the logical cache memory is compared with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 5
Dependent Claim
173 words
A data processor comprising: a logical cache memory containing logical address information as search information, a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer, the logical cache memory also containing physical address information corresponding to the logical address information in a cache entry, wherein the physical address contained in the cache entry thus selected is utilized for the generation of a physical address for write processing when the cache entry selected by the search information corresponds to a desired logical address, wherein when a cache entry selected by the search information from the logical cache memory does not correspond to the desired logical address, each of the physical address information contained in the logical cache memory is compared with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 6
Dependent Claim
237 words
A data processor comprising: a logical cache memory containing a plurality of entries, each entry containing a logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; wherein each entry of the logical cache memory also contains a physical address information corresponding to the logical address information in that cache entry; wherein the control unit includes: a cache address comparator for detecting that the cache entry selected by the search information from the logical cache memory does not correspond to a desired logical address, a physical address comparator for comparing each of the physical address information contained in the logical cache memory with physical address information resulting from the translation of the search information by the translation lookaside buffer to detect coincidence therebetween based on the detection made by the cache address comparator, a data controller for utilizing the information contained in the cache entry detected as a cache-hit when the comparison made by the physical address comparator results in coincidence, and an address controller for utilizing the physical address contained in the cache entry detected as a cache-hit for the generation of a physical address for write processing when the cache entry selected by the search information from the logical cache memory corresponds to the desired logical address.
Claim 7
Dependent Claim
237 words
A data processor comprising: a logical cache memory containing a plurality of entries, each entry containing a logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; wherein each entry of the logical cache memory also contains a physical address information corresponding to the logical address information in that cache entry; wherein the control unit includes: a cache address comparator for detecting that the cache entry selected by the search information from the logical cache memory does not correspond to a desired logical address, a physical address comparator for comparing each of the physical address information contained in the logical cache memory with physical address information resulting from the translation of the search information by the translation lookaside buffer to detect coincidence therebetween based on the detection made by the cache address comparator, a data controller for utilizing the information contained in the cache entry detected as a cache-hit when the comparison made by the physical address comparator results in coincidence, and an address controller for utilizing the physical address contained in the cache entry detected as a cache-hit for the generation of a physical address for write processing when the cache entry selected by the search information from the logical cache memory corresponds to the desired logical address.
Claim 8
Dependent Claim
85 words
A data processor as claimed in claim 4, wherein the logical cache memory is in a set-associative form and wherein the cache entry also contains an address space identifier of a multiple logical address space, a share flag for indicating whether the logical address space specified by the address space identifier shares a physical address space with one or more other logical address spaces, logical page information, data corresponding to the logical address and physical page information as the information assigned to the physical address.
Claim 9
Dependent Claim
85 words
A data processor as claimed in claim 5, wherein the translation lookaside buffer is in the set-associative form and wherein its translation pair also contains an address space identifier of a multiple logical address space, a share flag for indicating whether the logical address space specified by the address space identifier shares a physical address space with one or more other logical address spaces, logical page information, data corresponding to the logical address and physical page information as the information assigned to the physical address.
Claim 10
Dependent Claim
41 words
A data processor as claimed in claim 6, wherein a second translation lookaside buffer in a full-associative form is used as another translation lookaside buffer in place of the translation lookaside buffer when a size of the logical page is altered.
Claim 11
Dependent Claim
25 words
A data processor as claimed in claim 4, wherein the desired logical address shares a physical address space with one or more other logical addresses.
Claim 12
Dependent Claim
178 words
A data processor formed on a semiconductor substrate comprising: a logical cache memory containing logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; the logical cache memory also containing physical address information corresponding to the logical address information in a cache entry; wherein the physical address contained in the cache entry thus selected is utilized for the generation of a physical address for write processing when the cache entry selected by the search information corresponds to a desired logical address, wherein when a cache entry selected by the search information from the logical cache memory does not correspond to the desired logical address, each of the physical address information contained in the logical cache memory is compared with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 13
Dependent Claim
178 words
A data processor formed on a semiconductor substrate comprising: a logical cache memory containing logical address information as search information; a translation lookaside buffer for storing a translation pair for translating a logical address into a physical address, and a control unit controlling the logical cache memory and the translation lookaside buffer; the logical cache memory also containing physical address information corresponding to the logical address information in a cache entry; wherein the physical address contained in the cache entry thus selected is utilized for the generation of a physical address for write processing when the cache entry selected by the search information corresponds to a desired logical address, wherein when a cache entry selected by the search information from the logical cache memory does not correspond to the desired logical address, each of the physical address information contained in the logical cache memory is compared with physical address information resulting from the translation of the search information by the translation lookaside buffer, wherein a cache-hit results if there is a coincidence between the compared physical address information.
Claim 14
Dependent Claim
85 words
A data processor as claimed in claim 9, wherein the logical cache memory is in a set-associative form and wherein the cache entry also contains an address space identifier of a multiple logical address space, a share flag for indicating whether the logical address space specified by the address space identifier shares a physical address space with one or more other logical address spaces, logical page information, data corresponding to the logical address and physics page information as the information assigned to the physical address.
Claim 15
Dependent Claim
85 words
A data processor as claimed in claim 10, wherein the translation lookaside buffer is in the set-associative form and wherein its translation pair also contains an address space identifier of a multiple logical address space, a share flag for indicating whether the logical address space specified by the address space identifier shares a physical address space with one or more other logical address spaces, logical page information, data corresponding to the logical address and physical page information as the information assigned to the physical address.
Claim 16
Dependent Claim
41 words
A data processor as claimed in claim 11, wherein a second translation lookaside buffer in a full-associative form is used as another translation lookaside buffer in place of the translation lookaside buffer when a size of the logical page is altered.
Claim 17
Dependent Claim
38 words
A data processor as claimed in claim 9, wherein the data processor further comprises a controller coupled to a bus external to the data processor, wherein the bus is coupled to main memory external to the data processor.
References Cited (Backward Citations)
US4332010A
Cited
US4400770A
Cited
US4873629A
Cited
US4797814A
Cited
JPH0221342A
Cited
US5623626A
Cited
US4926317A
Cited
JPH01302444A
Cited
US5148538A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |