US5956477A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for processing information in a microprocessor to facilitate debug and performance monitoring
Assignee: Samsung Electronics Co Ltd
•
Filing: 1996-11-25
•
Granted: 1999-09-21
•
Expires: 2016-11-25
Abstract
Abstract Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing. The invention may also include a method of processing information in a microprocessor to facilitate microprocessor testing operations, wherein system bus monitoring information is generated whenever system bus accesses occur. This information, or indicators derived from it, is communicated to a microprocessor testing state machine on-chip with the microprocessor. In yet other embodiments, the invention may include the steps of: generating microprocessor self-monitoring information at various times during the life cycle of an instruction; utilizing the microprocessor self-monitoring information both when it becomes available as well as later, after retirement of the associated instruction; generating system bus monitoring information whenever system bus accesses occur; and utilizing the system bus monitoring information when it becomes available.
Inventors
- 👤 Gregory L Ranson
- 👤 Gregg B Lesartre
- 👤 Russell C Brockmann
- 👤 Douglas B Hunt
- 👤 Steven T Mangelsdorf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:14
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
96 words
A method of processing information in a microprocessor wherein the life cycle for each instruction begins with the fetch process for the instruction and ends either when the instruction retires or when it becomes known that the instruction will not retire, said method comprising the steps of: at a first time during an instruction's life cycle, generating a first set of microprocessor self-monitoring information; storing information necessary to execute the instruction; storing said first set of microprocessor self-monitoring information; and associating said first set of microprocessor self-monitoring information with said information necessary to execute the instruction.
Claim 2
Independent Claim
96 words
A method of processing information in a microprocessor wherein the life cycle for each instruction begins with the fetch process for the instruction and ends either when the instruction retires or when it becomes known that the instruction will not retire, said method comprising the steps of: at a first time during an instruction's life cycle, generating a first set of microprocessor self-monitoring information; storing information necessary to execute the instruction; storing said first set of microprocessor self-monitoring information; and associating said first set of microprocessor self-monitoring information with said information necessary to execute the instruction.
Claim 3
Dependent Claim
52 words
The method of claim 1, further comprising the steps of: at a second time during the instruction's life cycle, generating a second set of microprocessor self-monitoring information; storing said second set of microprocessor self-monitoring information; and associating said second set of microprocessor self-monitoring information with said information necessary to execute the instruction.
Claim 4
Dependent Claim
26 words
The method of claim 1, further comprising the step of: if the instruction retires, utilizing said first set of microprocessor self-monitoring information in microprocessor testing operations.
Claim 5
Dependent Claim
28 words
The method of claim 2, further comprising the step of: if the instruction retires, utilizing said first and second sets of microprocessor self-monitoring information in microprocessor testing operations.
Claim 6
Dependent Claim
36 words
The method of claim 1, wherein said step of generating said first set of microprocessor self-monitoring information comprises comparing at least a portion of the instruction with at least a portion of an expected instruction pattern.
Claim 7
Dependent Claim
40 words
The method of claim 1, wherein said step of generating said first set of microprocessor self-monitoring information comprises comparing at least a portion of the address of the instruction with at least a portion of an expected instruction address pattern.
Claim 8
Dependent Claim
54 words
The method of claim 1, wherein said step of generating said first set of microprocessor self-monitoring information comprises the step of: if the instruction accesses data memory during its execution, comparing at least a portion of the data involved in the data memory access with at least a portion of an expected data pattern.
Claim 9
Dependent Claim
58 words
The method of claim 1, wherein said step of generating said first set of microprocessor self-monitoring information comprises the step of: if the instruction accesses data memory during its execution, comparing at least a portion of the address of the data involved in the data memory access with at least a portion of an expected data address pattern.
Claim 10
Dependent Claim
25 words
The method of claim 1, wherein said step of generating said first set of microprocessor self-monitoring information comprises generating execution profile information about the instruction.
Claim 11
Dependent Claim
36 words
The method of claim 2, wherein said step of generating said second set of microprocessor self-monitoring information comprises comparing at least a portion of the instruction with at least a portion of an expected instruction pattern.
Claim 12
Dependent Claim
40 words
The method of claim 2, wherein said step of generating said second set of microprocessor self-monitoring information comprises comparing at least a portion of the address of the instruction with at least a portion of an expected instruction address pattern.
Claim 13
Dependent Claim
54 words
The method of claim 2, wherein said step of generating said second set of microprocessor self-monitoring information comprises the step of: if the instruction accesses data memory during its execution, comparing at least a portion of the data involved in the data memory access with at least a portion of an expected data pattern.
Claim 14
Dependent Claim
58 words
The method of claim 2, wherein said step of generating said second set of microprocessor self-monitoring information comprises the step of: if the instruction accesses data memory during its execution, comparing at least a portion of the address of the data involved in the data memory access with at least a portion of an expected data address pattern.
Claim 15
Dependent Claim
25 words
The method of claim 2, wherein said step of generating said first set of microprocessor self-monitoring information comprises generating execution profile information about the instruction.
Claim 16
Dependent Claim
25 words
The method of claim 9, wherein said execution profile information comprises an indication of whether the fetching of the instruction caused an instruction cache miss.
Claim 17
Dependent Claim
25 words
The method of claim 9, wherein said execution profile information comprises an indication of whether the instruction caused a data cache miss during its execution.
Claim 18
Dependent Claim
19 words
The method of claim 9, wherein said execution profile information comprises an indication of whether the instruction was nullified.
Claim 19
Dependent Claim
31 words
The method of claim 9, wherein said execution profile information comprises an indication of whether the instruction was a branch instruction and the microprocessor predicted that the branch would be taken.
Claim 20
Dependent Claim
27 words
The method of claim 9, wherein said execution profile information comprises an indication of whether the instruction was a branch instruction and the branch was actually taken.
Claim 21
Dependent Claim
51 words
The method of claim 4, wherein said step of utilizing said first and second sets of microprocessor self-monitoring information in microprocessor testing operations comprises generating a set of overall match results, the inputs for generating said set of overall match results comprising said first and second sets of microprocessor self-monitoring information.
Claim 22
Dependent Claim
27 words
The method of claim 20, further comprising the step of communicating said set of overall match results to a state machine configured to facilitate microprocessor testing operations.
Claim 23
Dependent Claim
35 words
The method of claim 1, further comprising the step of: immediately after said first set of microprocessor self-monitoring information is generated, communicating information about it to a state machine configured to facilitate microprocessor testing operations.
Claim 24
Dependent Claim
65 words
The method of claim 2, further comprising the steps of: immediately after said first set of microprocessor self-monitoring information is generated, communicating first immediate information about it to a state machine configured to facilitate microprocessor testing operations; and immediately after said second set of microprocessor self-monitoring information is generated, communicating second immediate information about it to said state machine configured to facilitate microprocessor testing operations.
Claim 25
Dependent Claim
94 words
The method of claim 20, further comprising the steps of: immediately after said first set of microprocessor self-monitoring information is generated, communicating first immediate information about it to a state machine configured to facilitate microprocessor testing operations; immediately after said second set of microprocessor self-monitoring information is generated, communicating second immediate information about it to said state machine configured to facilitate microprocessor testing operations; and immediately after said set of overall match results is generated, communicating information about said set of overall match results to said state machine configured to facilitate microprocessor testing operations.
Claim 26
Independent Claim
56 words
A method of processing information in a microprocessor to facilitate microprocessor testing operations, the method comprising the steps of: whenever the microprocessor accesses the system bus, generating system bus monitoring information; and immediately after said system bus monitoring information is generated, communicating information about it to an on-chip state machine configured to facilitate microprocessor testing operations.
Claim 27
Independent Claim
56 words
A method of processing information in a microprocessor to facilitate microprocessor testing operations, the method comprising the steps of: whenever the microprocessor accesses the system bus, generating system bus monitoring information; and immediately after said system bus monitoring information is generated, communicating information about it to an on-chip state machine configured to facilitate microprocessor testing operations.
Claim 28
Dependent Claim
36 words
The method of claim 25, wherein said step of generating system bus monitoring information comprises comparing at least a portion of the data involved in the system bus access with an expected system bus data pattern.
Claim 29
Dependent Claim
38 words
The method of claim 25, wherein said step of generating system bus monitoring information comprises comparing at least a portion of the system bus address involved in the system bus access with an expected system bus address pattern.
Claim 30
Dependent Claim
22 words
The method of claim 25 wherein said system bus monitoring information comprises information pertaining to the purpose of the system bus access.
Claim 31
Independent Claim
139 words
A method of processing information in a microprocessor to facilitate microprocessor testing, wherein the life cycle for each instruction in the microprocessor begins with the fetch process for the instruction and ends either when the instruction retires or when it becomes known that the instruction will not retire, said method comprising the steps of: at a first time during an instruction's life cycle, generating a first set of microprocessor self-monitoring information; storing information necessary to execute the instruction; storing said first set of microprocessor self-monitoring information; associating said first set of microprocessor self-monitoring information with said information necessary to execute the instruction; whenever the microprocessor accesses the system bus, generating system bus monitoring information; and immediately after said system bus monitoring information is generated, communicating information about it to an on-chip state machine configured to facilitate microprocessor testing operations.
Claim 32
Independent Claim
139 words
A method of processing information in a microprocessor to facilitate microprocessor testing, wherein the life cycle for each instruction in the microprocessor begins with the fetch process for the instruction and ends either when the instruction retires or when it becomes known that the instruction will not retire, said method comprising the steps of: at a first time during an instruction's life cycle, generating a first set of microprocessor self-monitoring information; storing information necessary to execute the instruction; storing said first set of microprocessor self-monitoring information; associating said first set of microprocessor self-monitoring information with said information necessary to execute the instruction; whenever the microprocessor accesses the system bus, generating system bus monitoring information; and immediately after said system bus monitoring information is generated, communicating information about it to an on-chip state machine configured to facilitate microprocessor testing operations.
Claim 33
Dependent Claim
52 words
The method of claim 29, further comprising the steps of: at a second time during the instruction's life cycle, generating a second set of microprocessor self-monitoring information; storing said second set of microprocessor self-monitoring information; and associating said second set of microprocessor self-monitoring information with said information necessary to execute the instruction.
Claim 34
Dependent Claim
37 words
The method of claim 30, further comprising the step of: if the instruction retires, communicating information about said first and second sets of microprocessor self-monitoring information to said on-chip state machine configured to facilitate microprocessor testing operations.
References Cited (Backward Citations)
US3947823A
Cited
US4303990A
Cited
US4500993A
Cited
US4598385A
Cited
US4491907A
Cited
US4446514A
Cited
US4425643A
Cited
US4431928A
Cited
US4433413A
Cited
US4622669A
Cited
US4674089A
Cited
US4933897A
Cited
US4879646A
Cited
US4910417A
Cited
US5535331A
Cited
US4873666A
Cited
US4924468A
Cited
US4868822A
Cited
US4841232A
Cited
US5173619A
Cited
US4912630A
Cited
US4993027A
Cited
US5136590A
Cited
US5202976A
Cited
US4964033A
Cited
US5053700A
Cited
US5157673A
Cited
US4935719A
Cited
US5226149A
Cited
US5206948A
Cited
US5210862A
Cited
US5226153A
Cited
US5157781A
Cited
US5059942A
Cited
US5564041A
Cited
US5623500A
Cited
US5345580A
Cited
US5375228A
Cited
US5504755A
Cited
US5317711A
Cited
US5534798A
Cited
US5452437A
Cited
US5400345A
Cited
US5579251A
Cited
US5479652B1
Cited
US5479652A
Cited
US5425036A
Cited
US5450349A
Cited
US5327435A
Cited
US5555428A
Cited
US5528526A
Cited
US5418452A
Cited
US5561761A
Cited
US5442641A
Cited
US5590354A
Cited
US5526365A
Cited
US5586288A
Cited
US5640508A
Cited
US5640542A
Cited
US5579492A
Cited
US5473754A
Cited
US5548775A
Cited
US5566300A
Cited
US5488688A
Cited
US5557619A
Cited
US5475815A
Cited
US5532174A
Cited
US5530804A
Cited
US5630048A
Cited
US5606710A
Cited
US5613144A
Cited
US5699516A
Cited
US5519715A
Cited
US5598421A
Cited
US5550528A
Cited
US5606564A
Cited
US5541935A
Cited
US5644609A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |