US5157781A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processor test architecture
Assignee: NXP USA Inc
•
Filing: 1990-01-02
•
Granted: 1992-10-20
•
Expires: 2010-01-02
Abstract
Abstract A test architecture in a data processing system having a plurality of circuit portions, coupled via a communication bus. In the system, a dedicated test register is placed in predetermined circuit portions which each can then operate in a normal mode and a test mode. A central processing unit (CPU) may initiate a test operation in any of the circuit portions in response to software executing by writing an operand to a centralized test module. Operands are scanned into and out of a circuit portion being tested while the central processing unit is capable of performing non-test processing activites. The CPU may also test itself using a dedicated test register which can only cause the CPU to enter a test mode after the register is written to.
Inventors
- 👤 Wallace B. Harwood
- 👤 Mark W. McDermott
- 👤 Dennis K. Verbeek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701; G01R31/3181; G01R31/3185; G01R31/318505; G06F11/2221
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
370 words
In a data processing system having a plurality of circuit portions coupled via a communication bus wherein a predetermined one of said circuit portions operates in one of a data processing mode of operation for implementing a first plurality of predetermined data processing functions and a test mode of operation for testing the predetermined circuit portion, a test architecture of the data processing system comprising: a test storage means in the predetermined circuit portion and coupled to the communication bus, the test storage means storing control information which is used to control the predetermined circuit portion during the test mode of operation; a bus master coupled to the communication bus for implementing a second plurality of predetermined data processing functions, the bus master selectively asserting control of the communication bus by providing a control signal to the predetermined circuit portion which places the predetermined circuit portion in the test mode of operation the bus master also providing the control information to the test storage means; and a test module coupled to the communication bus for performing a test of the predetermined circuit portion in response to the bus master by: (1) scanning an input operand of a first predetermined bit length into the test storage means via a first conductor of the communication bus in response to a first scan enable signal provided by the test module to the predetermined circuit portion via a second conductor of the communication bus; and (2) scanning an output operand of a second predetermined bit length out of the test storage means via a third conductor of the communication bus in response to a second scan enable signal provided by the test module to the predetermined circuit portion via a fourth conductor of the communication bus, the first predetermined bit length having a different magnitude than the second predetermined bit length, each of the first, second, third, and fourth conductors being used for another predetermined function when the data processing system is not in the test mode of operation; said bus master being able to continue implementing the second plurality of predetermined data processing functions after providing the control signal and concurrent with the test module performing the test of the predetermined circuit portion.
Claim 2
Dependent Claim
370 words
In a data processing system having a plurality of circuit portions coupled via a communication bus wherein a predetermined one of said circuit portions operates in one of a data processing mode of operation for implementing a first plurality of predetermined data processing functions and a test mode of operation for testing the predetermined circuit portion, a test architecture of the data processing system comprising: a test storage means in the predetermined circuit portion and coupled to the communication bus, the test storage means storing control information which is used to control the predetermined circuit portion during the test mode of operation; a bus master coupled to the communication bus for implementing a second plurality of predetermined data processing functions, the bus master selectively asserting control of the communication bus by providing a control signal to the predetermined circuit portion which places the predetermined circuit portion in the test mode of operation the bus master also providing the control information to the test storage means; and a test module coupled to the communication bus for performing a test of the predetermined circuit portion in response to the bus master by: (1) scanning an input operand of a first predetermined bit length into the test storage means via a first conductor of the communication bus in response to a first scan enable signal provided by the test module to the predetermined circuit portion via a second conductor of the communication bus; and (2) scanning an output operand of a second predetermined bit length out of the test storage means via a third conductor of the communication bus in response to a second scan enable signal provided by the test module to the predetermined circuit portion via a fourth conductor of the communication bus, the first predetermined bit length having a different magnitude than the second predetermined bit length, each of the first, second, third, and fourth conductors being used for another predetermined function when the data processing system is not in the test mode of operation; said bus master being able to continue implementing the second plurality of predetermined data processing functions after providing the control signal and concurrent with the test module performing the test of the predetermined circuit portion.
Claim 3
Dependent Claim
29 words
The data processing system of claim 1 wherein the control signal is provided by the bus master by writing an operand from the bus master to the test module.
Claim 4
Dependent Claim
28 words
The data processing system of claim 1 wherein said bus master comprises a central processing unit wherein said data processing system is contained within a single integrated circuit.
Claim 5
Dependent Claim
42 words
The data processing system of claim 3 wherein said central processing unit comprises a test register used solely for a predetermined test of the central processing unit, the predetermined test of the central processing unit being initiated by the central processing unit.
Claim 6
Dependent Claim
22 words
The data processing system of claim 4 wherein said central processing unit initiates the predetermined test in response to execution of software.
Claim 7
Dependent Claim
52 words
The data processing system of claim 4 wherein said predetermined test of the central processing unit begins only after both generation of the control signal indicating that the central processing unit is to be tested and a subsequent write operation to the test register of the central processing unit of an operand.
Claim 8
Independent Claim
368 words
A method of implementing a test architecture in a data processing system having a plurality of circuit portions coupled via a communication bus, a predetermined one of the plurality of the circuit portions operating in one of a data processing mode of operation for implementing a first plurality of predetermined data processing functions and a test mode of operation for testing the predetermined circuit portion, comprising the steps of: providing a test storage means in the predetermined circuit portion, the test storage means being coupled to the communication bus and storing control information which is used to control the predetermined circuit portion; coupling a bus master to the communication bus, the bus master implementing a second plurality of data processing functions and asserting control of the communication bus by providing a control signal to the predetermined circuit portion which places the predetermined circuit portion in the test mode of operation, the bus master also providing the control information to the test storage means; coupling a test module to the communication bus for performing a predetermined test of the predetermined circuit portion by scanning an input operand of a first predetermined bit length into the test storage means via a first conductor of the communication bus in response to a first scan enable signal provided by the test module to the predetermined circuit portion via a second conductor of the communication bus, and scanning an output operand of a second predetermined bit length out of the test storage means via a third conductor of the communication bus in response to a second scan enable signal provided by the test module to the predetermined circuit portion via a fourth conductor of the communication bus, the first predetermined bit length having a different magnitude than the second predetermined bit length to be able to scan operands of differing bit lengths with the test storage means, and each of the first, second, third, and fourth conductors being used for another predetermined function when the data processing system is not in the test mode of operation; and continuing implementing the second plurality of data processing functions with said bus master concurrent with the test module performing the test of the predetermined circuit portion.
Claim 9
Independent Claim
368 words
A method of implementing a test architecture in a data processing system having a plurality of circuit portions coupled via a communication bus, a predetermined one of the plurality of the circuit portions operating in one of a data processing mode of operation for implementing a first plurality of predetermined data processing functions and a test mode of operation for testing the predetermined circuit portion, comprising the steps of: providing a test storage means in the predetermined circuit portion, the test storage means being coupled to the communication bus and storing control information which is used to control the predetermined circuit portion; coupling a bus master to the communication bus, the bus master implementing a second plurality of data processing functions and asserting control of the communication bus by providing a control signal to the predetermined circuit portion which places the predetermined circuit portion in the test mode of operation, the bus master also providing the control information to the test storage means; coupling a test module to the communication bus for performing a predetermined test of the predetermined circuit portion by scanning an input operand of a first predetermined bit length into the test storage means via a first conductor of the communication bus in response to a first scan enable signal provided by the test module to the predetermined circuit portion via a second conductor of the communication bus, and scanning an output operand of a second predetermined bit length out of the test storage means via a third conductor of the communication bus in response to a second scan enable signal provided by the test module to the predetermined circuit portion via a fourth conductor of the communication bus, the first predetermined bit length having a different magnitude than the second predetermined bit length to be able to scan operands of differing bit lengths with the test storage means, and each of the first, second, third, and fourth conductors being used for another predetermined function when the data processing system is not in the test mode of operation; and continuing implementing the second plurality of data processing functions with said bus master concurrent with the test module performing the test of the predetermined circuit portion.
Claim 10
Dependent Claim
24 words
The method of claim 7 further comprising the step of: implementing the bus master as a central processing unit of the data processing system.
References Cited (Backward Citations)
US3562716A
Cited
US3415981A
Cited
US4384322A
Cited
US4245307A
Cited
US4315313A
Cited
US4385382A
Cited
US4488299A
Cited
US4489414A
Cited
US4622669A
Cited
US4797885A
Cited
US4816997A
Cited
US4857348A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |