US4245307A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controller for data processing system
Assignee: Formation Inc California
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Filing: 1979-09-14
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Granted: 1981-01-13
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Expires: 1999-09-14
Abstract
Abstract A controller for at least one secondary storage device for use in a data processing system having a system bus which accommodates a device or a CPU that first acquires control, a device bus that has the same address, data and control format as the system bus and a cache bus which maintains its own timing for address and data signals. The controller has means for transferring the control signals between the device bus and the system bus to establish control over the system bus by the secondary storage device. The data, address and control signals are transferred between the device bus and the cache bus in accordance with the cache bus timing.
Inventors
- 👤 Charles L. Kapeghian
- 👤 Charles C. Garman
- 👤 Paul R. Malnati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/20; G06F13/28; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
325 words
A controller system for use in a data processing system having a CPU, a main memory, a high speed memory and a cache bus, the controller system having a high speed controller, a drive controller and a device bus coupled to and between said high speed controller and said drive controller for handling data, address and control signals, said drive controller coupled to a plurality of secondary storage devices each having storage media, the system bus coupled to and between the CPU and the high speed controller and having the same data, address and control formats as the device bus where said data is the data stored on the device storage media, the high speed memory coupled to and between the CPU and the main memory, and the cache bus coupled to and between the high speed memory and the high speed controller for handling data, address and control signals comprising (a) (1) means for varying the timing of the control and address signals provided by the drive controller on the device bus for timing compatibility with the control and address signals on the system bus whereby the drive controller seizes control over the system bus to initiate a transfer of data between the storage devices and the system bus, (2) the drive controller including means for assembling and reformatting bytes of data from the storage media and producing address and control signals in the format of the system bus whereby such data is transferred between the storage devices and the system bus, (b) (1) means for varying the timing of the control and address signals provided by the system bus when the drive controller has relinquished control over the system bus upon completion of said data transfer, (2) said drive controller including means for accepting address and control signals in the format of the system bus, and (c) means for transferring address, data and control signals between the device bus and the cache bus.
Claim 2
Dependent Claim
325 words
A controller system for use in a data processing system having a CPU, a main memory, a high speed memory and a cache bus, the controller system having a high speed controller, a drive controller and a device bus coupled to and between said high speed controller and said drive controller for handling data, address and control signals, said drive controller coupled to a plurality of secondary storage devices each having storage media, the system bus coupled to and between the CPU and the high speed controller and having the same data, address and control formats as the device bus where said data is the data stored on the device storage media, the high speed memory coupled to and between the CPU and the main memory, and the cache bus coupled to and between the high speed memory and the high speed controller for handling data, address and control signals comprising (a) (1) means for varying the timing of the control and address signals provided by the drive controller on the device bus for timing compatibility with the control and address signals on the system bus whereby the drive controller seizes control over the system bus to initiate a transfer of data between the storage devices and the system bus, (2) the drive controller including means for assembling and reformatting bytes of data from the storage media and producing address and control signals in the format of the system bus whereby such data is transferred between the storage devices and the system bus, (b) (1) means for varying the timing of the control and address signals provided by the system bus when the drive controller has relinquished control over the system bus upon completion of said data transfer, (2) said drive controller including means for accepting address and control signals in the format of the system bus, and (c) means for transferring address, data and control signals between the device bus and the cache bus.
Claim 3
Dependent Claim
40 words
The controller system of claim 1 in which there is provided timing and control interface means coupled between the device bus and the cache bus for transferring address, control and data signals between said device bus and said cache bus.
Claim 4
Dependent Claim
49 words
The controller system of claim 2 in which said timing and control interface means includes first gating means for detecting when the cache bus is ready to accept data, and therefore causing the high speed controller to gate out temporarily stored device data for transfer to the cache bus.
Claim 5
Dependent Claim
23 words
The controller system of claim 3 in which there is provided first register means for providing said temporary storage of said device data.
Claim 6
Dependent Claim
56 words
The controller system of claim 2 in which said timing and control interface means includes second gating means for detecting when the cache bus is ready to transfer data to the device, and thereafter causing the high speed controller to accept data from the cache bus for temporary storage and then for transfer to the device.
Claim 7
Dependent Claim
23 words
The controller system of claim 5 in which there is provided second register means for providing said temporary storage of said cache data.
Claim 8
Dependent Claim
33 words
The controller system of claim 1 in which said drive controller includes means for producing status and error information for the CPU when the drive controller has relinquished control over the system bus.
Claim 9
Dependent Claim
42 words
The controller system of claim 1 in which there is provided gating means for selectively transferring and temporarily storing data from the device bus for transfer to the system bus in accordance with the timing requirements of the device and system busses.
Claim 10
Dependent Claim
31 words
The controller system of claim 1 in which there is provided means for changing an address format from the device bus into a corresponding address format required by said cache bus.
Claim 11
Dependent Claim
40 words
The controller system of claim 9 in which said address changing means includes address extension registers for storing the information necessary to extend said address format received from the device bus into corresponding address format required by the cache bus.
Claim 12
Dependent Claim
56 words
The controller system of claim 1 in which there is provided means for converting the data word format of the device bus into a corresponding data word format required by the cache bus, and means for converting the data word format of said cache bus into a corresponding data word format required by said device bus.
Claim 13
Dependent Claim
36 words
The controller system of claim 11 in which said converting means includes means for changing a single word format of the data of the device bus into a double word format required by the cache bus.
Claim 14
Dependent Claim
33 words
The controller system of claim 12 in which said converting means includes means for changing a byte of data from the device bus into a double word format required by the cache bus.
Claim 15
Dependent Claim
60 words
The controller system of claim 13 in which there is provided register means for loading bytes of data from said device bus into said register means and for transferring the data to said cache bus when said register means is full, and additional register means for loading bytes of data from said cache bus awaiting transfer to said device bus.
Claim 16
Dependent Claim
35 words
The controller system of claim 12 in which there is provided multiplex means for splitting the data format used by the cache bus into bytes for controlling the transfer of data onto the device bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |