US4622669A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test module for asynchronous bus
Assignee: Motorola Solutions Inc
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Filing: 1985-03-04
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Granted: 1986-11-11
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Expires: 2005-03-04
Abstract
Abstract A test module is provided for troubleshooting and diagnosing hardware failures in the interface logic to an asynchronous microprocessor bus at true operating speed until a fault occurs. If a fault is detected, the circuit will halt a microprocessor under test coupled to the asynchronous microprocessor bus and freeze the state of the bus signal lines. The microprocessor under test has bit pattern sets therein. A test microprocessor has test pattern sets stored in internal memory. Test pattern latches are coupled to the test microprocessor for sequentially latching the test pattern sets. Address bus latches and data bus latchs are coupled to the asynchronous bus for latching the state of the address lines as a pattern under test. A comparator is coupled to the asynchronous bus, the test microprocessor, the first means, and the second means, for comparing one of the bit patterns to one of the test patterns wherein a continue signal is supplied to the asynchronous bus and the test microprocessor when the test pattern and the bit pattern are the same so that another of the test patterns and another of the bit patterns may be compared. A diagnose signal is supplied to the test microprocessor when the test pattern and the bit pattern are not the same. Fault latches are coupled to the address bus latches and data bus latches, the test microprocessor, and the asynchronous bus, for outputting the bit pattern when the diagnose signal is generated.
Inventors
- 👤 Shlomo Pri-Tal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:53
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
254 words
A test module for diagnosing an asynchronous microprocessor bus, said asynchronous microprocessor bus having a plurality of signal lines, and a microprocessor under test coupled to said asynchronous bus, comprising: a test microprocessor having a plurality of test patterns; first means coupled to said test microprocessor for sequentially latching said test patterns; second means coupled to said asynchronous bus for sequentially latching the state of said plurality of signal lines as a bit pattern; third means coupled to said asynchronous bus, said test microprocessor, said first means, and said second means, for comparing one of said bit patterns to one of said test patterns wherein a continue signal is supplied to said asynchronous bus and said test microprocessor when said test pattern and said bit pattern are the same, said continue signal causing said test microprocessor to supply another of said test patterns and said microprocessor under test to supply another of said bit patterns for comparison, and wherein a diagnose signal is supplied to said test microprocessor when said test pattern and said bit pattern are not the same; and fourth means coupled to said second means and said test microprocessor for transmitting said bit pattern from said second means to said test microprocessor when said diagnose signal is generated, whereby in absence of said continue signal said microprocessor under test maintains said diagnose signal causing the state of said bit pattern within said asynchronous bus, and said diagnose signal causes said test microprocessor to diagnose said bit pattern and provide an output.
Claim 2
Dependent Claim
254 words
A test module for diagnosing an asynchronous microprocessor bus, said asynchronous microprocessor bus having a plurality of signal lines, and a microprocessor under test coupled to said asynchronous bus, comprising: a test microprocessor having a plurality of test patterns; first means coupled to said test microprocessor for sequentially latching said test patterns; second means coupled to said asynchronous bus for sequentially latching the state of said plurality of signal lines as a bit pattern; third means coupled to said asynchronous bus, said test microprocessor, said first means, and said second means, for comparing one of said bit patterns to one of said test patterns wherein a continue signal is supplied to said asynchronous bus and said test microprocessor when said test pattern and said bit pattern are the same, said continue signal causing said test microprocessor to supply another of said test patterns and said microprocessor under test to supply another of said bit patterns for comparison, and wherein a diagnose signal is supplied to said test microprocessor when said test pattern and said bit pattern are not the same; and fourth means coupled to said second means and said test microprocessor for transmitting said bit pattern from said second means to said test microprocessor when said diagnose signal is generated, whereby in absence of said continue signal said microprocessor under test maintains said diagnose signal causing the state of said bit pattern within said asynchronous bus, and said diagnose signal causes said test microprocessor to diagnose said bit pattern and provide an output.
Claim 3
Dependent Claim
134 words
The test module according to claim 1 wherein said second means comprises: a plurality of address latches coupled to said asynchronous bus, said third means and said fourth means, said plurality of address latches latching an address pattern as a first portion of said bit pattern; a plurality of data latches coupled to said asynchronous bus, said third means, and said fourth means, said plurality of data latches latching a data pattern as a second portion of said bit pattern; and a signal line selector coupled to said asynchronous bus, said plurality of address latches, and said plurality of data latches for enabling either said plurality of address latches or said plurality of data latches for selectively feeding said address pattern or said data pattern, respectively, to said third means and said fourth means.
Claim 4
Dependent Claim
73 words
The test module according to claim 2 wherein said first means comprises: a plurality of test pattern latches coupled to said test microprocessor and said third means; an address decoder coupled to said test microprocessor, said plurality of test pattern latches, and said fourth means, said address decoder either enabling said plurality of test pattern latches when said continue signal is generated or enabling said fourth means when said diagnose signal is generated.
Claim 5
Dependent Claim
151 words
The test module according to claim 3 wherein said third means comprises: a plurality of comparators coupled to said plurality of address latches, said plurality of data latches, said plurality of test pattern latches, said asynchronous bus, and said test microprocessor, for supplying said continue signal to said asynchronous bus and said test microprocessor when said bit pattern is the same as said test pattern, and supplying said diagnose signal to said test microprocessor when said bit pattern is not the same as said test pattern; and a test synchronizer coupled to said asynchronous bus, said test microprocessor, and said comparators, for supplying a compare enable signal to said comparators when a first signal is received from said asynchronous bus and a second signal is received from said test microprocessor, said first signal and said second signal indicating when said bit pattern and said test pattern, respectively, are available for comparison.
Claim 6
Dependent Claim
38 words
The test module according to claim 4 wherein said fourth means comprises a plurality of fault latches for latching said bit pattern and, when said diagnose signal is generated, feeding said latched bit pattern to said test microprocessor.
Claim 7
Independent Claim
153 words
A method of diagnosing an asynchronous bus having a plurality of signal lines, said asynchronous bus coupled to a first microprocessor, comprising the steps of: latching the state of the signal lines as a bit pattern; latching a test pattern from a test microprocessor; comparing the bit pattern to the test pattern; generating a continue signal to the test microprocessor and the first microprocessor when the bit pattern is the same as the test pattern so that another bit pattern is compared to another test pattern; generating a diagnose signal to the test microprocessor when the bit pattern is not the same as the test pattern; said first microprocessor maintaining the state of the signal lines and preserving the bit pattern within the asynchronous bus in absence of the continue signal when the diagnose signal is generated; and diagnosing the preserved bit pattern by the test microprocessor when the diagnose signal is generated.
Claim 8
Independent Claim
153 words
A method of diagnosing an asynchronous bus having a plurality of signal lines, said asynchronous bus coupled to a first microprocessor, comprising the steps of: latching the state of the signal lines as a bit pattern; latching a test pattern from a test microprocessor; comparing the bit pattern to the test pattern; generating a continue signal to the test microprocessor and the first microprocessor when the bit pattern is the same as the test pattern so that another bit pattern is compared to another test pattern; generating a diagnose signal to the test microprocessor when the bit pattern is not the same as the test pattern; said first microprocessor maintaining the state of the signal lines and preserving the bit pattern within the asynchronous bus in absence of the continue signal when the diagnose signal is generated; and diagnosing the preserved bit pattern by the test microprocessor when the diagnose signal is generated.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-10 | 1990-05-12 | 1990-11-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-10 | 1994-05-12 | 1994-11-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-10 | 1998-05-12 | 1998-11-11 | $7700.00 | Window Closed / Lapsed |