US5644609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for reading and writing remote registers on an integrated circuit chip using a minimum of interconnects
Assignee: Hewlett Packard Enterprise Development LP
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Filing: 1996-07-31
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Granted: 1997-07-01
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Expires: 2016-07-31
Abstract
Abstract A method and apparatus is disclosed for reading data from and writing data to remote registers that are dispersed throughout an integrated circuit chip. Regardless of the size or number of remote registers involved, the operation is accomplished using only two interconnect lines, plus a clock. Each remote register is associated with a unique address. During a write operation, a microprocessor loads the write data into a staging register, loads the destination address into a header generation register along with a read/write control bit, and loads a count value into a clock. Thereafter, the apparatus of the invention proceeds automatically, as the clock counts down, to shift the data onto a serial data line following a header. Each of the remote registers in the system are arranged serially, and each monitors the header information, comparing the address contained in the header with its own address. In the event of a match, the remote register selected is enabled to shift data serially into itself from the serial data line. During a read operation, the selected remote register shifts its data out onto the serial data line. The read data is ultimately shifted back into the staging register.
Inventors
- 👤 John W. Bockhaus
- 👤 Gregg B. Lesartre
- 👤 Gregory L. Ranson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:46
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G11; G11C; G11C19/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
184 words
A system of registers implemented on an integrated circuit chip, comprising: a staging register circuitry having a staging register circuitry control signal output, a staging register circuitry serial data output, and a staging register circuitry serial data input; a series of remote register circuitries, each remote register circuitry in said series having at least one data latch for propagating data from a remote register circuitry serial data input to a remote register circuitry serial data output, and each remote register circuitry in said series having at least one control signal latch for propagating a control signal from a remote register circuitry control signal input to a remote register circuitry control signal output; a serial data line exiting said staging register circuitry at said staging register circuitry serial data output, propagating through each of said remote register circuitries in said series and reentering said staging register circuitry at said staging register circuitry serial data input; and a control signal line exiting said staging register circuitry at said staging register circuitry control signal output and propagating through each of said remote register circuitries in said series.
Claim 2
Independent Claim
184 words
A system of registers implemented on an integrated circuit chip, comprising: a staging register circuitry having a staging register circuitry control signal output, a staging register circuitry serial data output, and a staging register circuitry serial data input; a series of remote register circuitries, each remote register circuitry in said series having at least one data latch for propagating data from a remote register circuitry serial data input to a remote register circuitry serial data output, and each remote register circuitry in said series having at least one control signal latch for propagating a control signal from a remote register circuitry control signal input to a remote register circuitry control signal output; a serial data line exiting said staging register circuitry at said staging register circuitry serial data output, propagating through each of said remote register circuitries in said series and reentering said staging register circuitry at said staging register circuitry serial data input; and a control signal line exiting said staging register circuitry at said staging register circuitry control signal output and propagating through each of said remote register circuitries in said series.
Claim 3
Dependent Claim
78 words
A system of registers according to claim 1, wherein said staging register circuitry further comprises: header generation circuitry for propagating information on said control signal and serial data lines to select at least one of said remote register circuitries; and wherein each of the remote register circuitries in said series further comprises: a remote register; and header capture circuitry for determining, responsive to information propagated on said control signal and serial data lines, whether it has been selected.
Claim 4
Independent Claim
142 words
A method of writing data to one remote register out of a group of remote registers in an integrated circuit chip using a minimum of interconnect lines, said method comprising the steps of: associating a unique address with each remote register in said group of remote registers; loading said data into a staging register; serially shifting, onto a serial data line coupled to each remote register in said group of remote registers, header bits corresponding to the address of the remote register sought to be written; serially shifting, onto said serial data line, said data from said staging register; at each remote register in said group of remote registers, determining whether the address in the header bits corresponds to the unique address associated with this remote register and, if so, shifting said data from said serial data line into this remote register.
Claim 5
Independent Claim
142 words
A method of writing data to one remote register out of a group of remote registers in an integrated circuit chip using a minimum of interconnect lines, said method comprising the steps of: associating a unique address with each remote register in said group of remote registers; loading said data into a staging register; serially shifting, onto a serial data line coupled to each remote register in said group of remote registers, header bits corresponding to the address of the remote register sought to be written; serially shifting, onto said serial data line, said data from said staging register; at each remote register in said group of remote registers, determining whether the address in the header bits corresponds to the unique address associated with this remote register and, if so, shifting said data from said serial data line into this remote register.
Claim 6
Independent Claim
135 words
A method of reading data from one remote register out of a group of remote registers in an integrated circuit chip using a minimum of interconnect lines, said method comprising the steps of: associating a unique address with each remote register in said group of remote registers; serially shifting, onto a serial data line coupled to each remote register in said group of remote registers, header bits corresponding to the address of the remote register sought to be written; at each remote register in said group of remote registers, determining whether the address in the header bits corresponds to the unique address associated with this remote register and, if so, shifting the data from this remote register onto said serial data line; and shifting the data from said serial data line into a staging register.
Claim 7
Independent Claim
135 words
A method of reading data from one remote register out of a group of remote registers in an integrated circuit chip using a minimum of interconnect lines, said method comprising the steps of: associating a unique address with each remote register in said group of remote registers; serially shifting, onto a serial data line coupled to each remote register in said group of remote registers, header bits corresponding to the address of the remote register sought to be written; at each remote register in said group of remote registers, determining whether the address in the header bits corresponds to the unique address associated with this remote register and, if so, shifting the data from this remote register onto said serial data line; and shifting the data from said serial data line into a staging register.
References Cited (Backward Citations)
US4648105A
Cited
US5134638A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |