US4491907A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Plurality of processors sharing the memory, the arithmetic logic unit and control circuitry all on a single semiconductor chip
Assignee: Texas Instruments Inc
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Filing: 1980-12-15
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Granted: 1985-01-01
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Expires: 2000-12-15
Abstract
Abstract An electronic digital processing system implemented on a single MOS/LSI semiconductor chip including a ROM for storing instruction codes, a RAM for storing data, an arithmetic logic unit for performing operations on data under control of microinstructions or commands, control circuitry for generating commands in response to the instruction codes in a plurality of central processing units. The fetching of instructions from the ROM, the accessing of data from the RAM, the operation of the arithmetic unit are controlled by the central processing units which share the same data paths that couple the central processing units to the ROM, RAM, arithmetic unit and control circuitry.
Inventors
- 👤 Peter L. Koeppen
- 👤 Gerald Rogers
- 👤 Sammy K. Brown
- 👤 Duane Solimeno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:31
CPC Classifications
H; H04; H04M; H04M1/00; H04M1/64; G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
175 words
An electronic digital processor system comprising: a semiconductor unit; a memory in said unit for storing instructions; an arithmetic and logic means in said unit for performing operations under control of commands derived from said instructions; control circuitry in said unit for obtaining from said memory said instructions; input means in said unit for receiving a data; output means in said unit for displaying said data; a first central processor in said unit for executing said instructions using said memory, said arithmetic and logic means, said control circuitry, said input means, said output means and data paths which connect said first central processor to said memory, said arithmetic and logic means, said control circuitry, said input means and said output means; a second central processor in said unit for executing said instructions simultaneously with and independent from execution of instructions by said first central processor, sharing said memory, said arithmetic and logic means, said control circuitry, said input means and said output means with said first central processor while also connected to said data paths.
Claim 2
Dependent Claim
175 words
An electronic digital processor system comprising: a semiconductor unit; a memory in said unit for storing instructions; an arithmetic and logic means in said unit for performing operations under control of commands derived from said instructions; control circuitry in said unit for obtaining from said memory said instructions; input means in said unit for receiving a data; output means in said unit for displaying said data; a first central processor in said unit for executing said instructions using said memory, said arithmetic and logic means, said control circuitry, said input means, said output means and data paths which connect said first central processor to said memory, said arithmetic and logic means, said control circuitry, said input means and said output means; a second central processor in said unit for executing said instructions simultaneously with and independent from execution of instructions by said first central processor, sharing said memory, said arithmetic and logic means, said control circuitry, said input means and said output means with said first central processor while also connected to said data paths.
Claim 3
Dependent Claim
45 words
An electronic digital processor system according to claim 1, wherein said data paths includes independent data paths for the transmission of data between said central processors and said memory means, said input means, said output means, said arithmetic and logic means, and said control circuitry.
Claim 4
Dependent Claim
22 words
An electronic digital processor system according to claim 2, wherein said memory means consists of read-only memory means and random-access memory means.
Claim 5
Dependent Claim
20 words
An electronic digital processor system according to claim 3, wherein said random-access memory means is addressed by said central processors.
Claim 6
Dependent Claim
20 words
An electronic digital processor system according to claim 4 wherein said read-only memory means is addressed by said central processors.
Claim 7
Dependent Claim
33 words
An electronic digital processor system according to claim 5, wherein each central processor includes storage means provided for recording data from said arithmetic and logic means and coupled to said random-access memory means.
Claim 8
Dependent Claim
37 words
An electronic digital processor system according to claim 6, wherein each central processor includes a accumulator register provided to receive data from said arithmetic and logic means and coupled to input of said arithmetic and logic means.
Claim 9
Dependent Claim
22 words
An electronic digital processor system according to claim 5, wherein said arithmetic and logic means receives data from said central processors independently.
Claim 10
Dependent Claim
25 words
An electronic digital processor according to claim 8, wherein said input means includes first and second input terminals for providing data to said central processors.
Claim 11
Dependent Claim
78 words
An electronic digital processor system according to claim 9, wherein said output means includes first, second, and third output terminals, first output terminal connected to first and second central processor for outputting data from either said first central processor or said second central processor, second output terminal connected to said first central processor for outputting data from said first central processor, third output terminal connected to said second central processor for outputting data from said second central processor.
Claim 12
Dependent Claim
20 words
An electronic digital processor system according to claim 10, wherein second input terminal is connected to said third output terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |