Multi-processor data processing system

Claim 2

An improved data processing system, comprising: a. a plurality of data processor means for executing data processing tasks on and in response to received digital information, said plurality of data processor means including shared common resource circuit means comprising data storage means, arithmetic and logic means, and timing and control means, said plurality of data processor means further having circuit means responsive to said execution of tasks by each of said data processor means for generating request output signals indicative of real time requirements for use of said common resource circuit means by each of said data processor means in executing its respective said data processing tasks, b. input/output circuit means operatively connecting at least one of said plurality of data processor means with external sources for transfer of said digital information therebetween; c. basic timing circuit means for generating major cycle timing signals wherein the duration of a major cycle approximates one or more storage reference cycles of said data processing system up to that period of time required by said system to execute an instruction; and d. processor control means in circuit with said plurality of data processor means and with said basic timing means for discriminately allocating operative use of said common resource circuit means among said plurality of data processor means, comprising: i. priority circuit means operatively connected to receive said plurality of request output signals for determining therefrom relative real time needs of said plurality of data processor means for their respective operative use of said common resource circUit means and for generating need determination output signals in response thereto; and ii. activating means operatively connected to receive said need determination output signals and responsive thereto and to said major cycle timing signals for selectively allocating operative use of said common resource circuit means among said plurality of data processor means on said major cycle time period basis according to said relative needs determination.

Claim 3

An improved data processing system according to claim 1, wherein said activating means of said processor control means includes means for selectively activating at least one of said data processor means once each said major cycle time period.

Claim 4

timing and control circuit means responsive to said major cycle timing signals for providing timing and control signals to electrical networks within said central processor, said storage means and said input/output means on said major cycle time period basis;

Claim 5

timing and control circuit means responsive to said major cycle timing signals for providing timing and control signals to electrical networks within said central processor, said storage means and said input/output means on said major cycle time period basis;

Claim 6

timing and control circuit means responsive to said major cycle timing signals for providing timing and control signals to electrical networks within said central processor, said storage means and said input/output means on said major cycle time period basis;

Claim 7

timing and control circuit means responsive to said major cycle timing signals for providing timing and control signals to electrical networks within said central processor, said storage means and said input/output means on said major cycle time period basis;

Claim 8

arithmetic and logic circuit means for transferring, responsive to said timing and control signals said digital information between said input/output means and said storage means and for performing thereon and in response thereto arithmetic, logical and other manipulative operations;

Claim 9

arithmetic and logic circuit means for transferring, responsive to said timing and control signals said digital information between said input/output means and said storage means and for performing thereon and in response thereto arithmetic, logical and other manipulative operations;

Claim 10

An improved data processing system according to claim 1, wherein said priority circuit means of said processor control means includes means for ordering said plurality of received request output signals according to a predetermined priority schedule and for generating said need determination output signals responsive to said schedule.

Claim 11

arithmetic and logic circuit means for transferring, responsive to said timing and control signals, said digital information between said input/output means and said storage means and for performing thereon arithmetic, logical and other manipulative operations;

Claim 12

arithmetic and logic circuit means for transferring, responsive to said timing and control signals, said digital information between said input/output means and said storage means and for performing thereon arithmetic, logical and other manipulative operations;

Claim 13

register file circuits, including a plurality of dedicated register groups, and means for operatively connecting said dedicated register groups to share said arithmetic and logic circuit means, said storage means and said timing and control circuit means to form a plurality of data processing means, one each of said data processing means being activated by the operative connection of one of said dedicated register groups with said shared arithmetic and logic circuit means, said storage means and said timing and control circuit means, wherein each of said data processing means is operable when activated to independently execute data processing tasks on and in response to said digital information; and

Claim 14

register file circuits, including a plurality of dedicated register groups, and means for operatively connecting said dedicated register groups to share said arithmetic and logic circuit means, said storage means and said timing and control circuit means to form a plurality of data processing means, one each of said data processing means being activated by the operative connection of one of said dedicated register groups with said shared arithmetic and logic circuit means, said storage means and said timing and control circuit means, wherein each of said data processing means is operable when activated to independently execute data processing tasks on and in response to said digital information; and

Claim 15

An improved data processing system according to claim 1, wherein each of said plurality of data processor means includes a plurality of distinct register circuit groups, each of said register circuit groups being operatively dedicated to a different one of said plurality of data processor means.

Claim 16

register file circuit means, including a plurality of dedicated register groups each operatively connected to share said arithmetic and logic circuit means, said storagE means and said timing and control circuit means, for independently performing a data processing task on and in response to said digital information, wherein each of said register groups is operatively connectable with and disconnectable from said arithmetic and logic circuit means, said storage means and said timing and control circuit means, without loss of that transient data associated with said register group in the operative execution of its said data processing task; and

Claim 17

register file circuit means, including a plurality of dedicated register groups each operatively connected to share said arithmetic and logic circuit means, said storagE means and said timing and control circuit means, for independently performing a data processing task on and in response to said digital information, wherein each of said register groups is operatively connectable with and disconnectable from said arithmetic and logic circuit means, said storage means and said timing and control circuit means, without loss of that transient data associated with said register group in the operative execution of its said data processing task; and

Claim 18

means responsive to said major cycle timing signals for selectively operatively connecting one of said plurality of dedicated register groups at a time with said arithmetic and logic circuit means, said storage means and said timing and control circuit means on said major cycle time period basis, causing said data processing task associated with that connected dedicated register group to be executed on said major cycle time period basis.

Claim 19

means responsive to said major cycle timing signals for selectively operatively connecting one of said plurality of dedicated register groups at a time with said arithmetic and logic circuit means, said storage means and said timing and control circuit means on said major cycle time period basis, causing said data processing task associated with that connected dedicated register group to be executed on said major cycle time period basis.

Claim 20

An improved data processing system, comprising: a. a plurality of data processor means for executing data processing tasks on and in response to received digital information, said plurality of data processor means including shared common resource circuit means comprising data storage means, arithmetic and logic means, and timing and control means, said plurality of data processor means further having circuit means responsive to said execution of tasks by each of said data processor means for generating request output signals indicative of real time requirements for use of said common resource circuit means by each of said data processor means in executing its respective said data processing tasks; b. input/output circuit means operatively connecting at least one of said plurality of said data processor means with external sources for transfer of said digital information therebetween; c. basic timing circuit means for generating major cycle timing signals wherein the duration of a major cycle approximates one or more storage reference cycles of said data processing system up to that period of time required by said system to execute an instruction; and d. processor control means in circuit with said plurality of data processor means and with said basic timing circuit means, operatively connected to receive said plurality of request output signals and said major cycle timing signals and being responsive thereto for selectively allocating on said major cycle time period basis operative use of said common resource circuit means sequentially among the part of said plurality of said data processor means which require operative use of said common resource circuit means at an instance in time, as indicated by said plurality of request output signals.

Claim 21

An improved data processing system, comprising: a. a plurality of data processor means for executing data processing tasks on and in response to received digital information, said plurality of data processor means including shared common resource circuit means comprising data storage means, arithmetic and logic means, and timing and control means, said plurality of data processor means further having circuit means responsive to said execution of tasks by each of said data processor means for generating request output signals indicative of real time requirements for use of said common resource circuit means by each of said data processor means in executing its respective said data processing tasks; b. input/output circuit means operatively connecting at least one of said plurality of said data processor means with external sources for transfer of said digital information therebetween; c. basic timing circuit means for generating major cycle timing signals wherein the duration of a major cycle approximates one or more storage reference cycles of said data processing system up to that period of time required by said system to execute an instruction; and d. processor control means in circuit with said plurality of data processor means and with said basic timing circuit means, operatively connected to receive said plurality of request output signals and said major cycle timing signals and being responsive thereto for selectively allocating on said major cycle time period basis operative use of said common resource circuit means sequentially among the part of said plurality of said data processor means which require operative use of said common resource circuit means at an instance in time, as indicated by said plurality of request output signals.

Claim 22

resource allocation circuit means operatively connected with said timing and control circuit means and with said plurality of data processing means for monitoring activation requirements of said plurality of data processing means in the performance of their respective said data processing tasks and responsive thereto and to said major cycle timing signals for automatically selectively activating on a priority basis at least one of said data processing means on said major cycle time period basis.

Claim 23

resource allocation circuit means operatively connected with said timing and control circuit means and with said plurality of data processing means for monitoring activation requirements of said plurality of data processing means in the performance of their respective said data processing tasks and responsive thereto and to said major cycle timing signals for automatically selectively activating on a priority basis at least one of said data processing means on said major cycle time period basis.

Claim 24

In a reconfigured data processing system having: input/output means for receiving and transmitting information from and to external sources; basic timing circuit means for generating major cycle timing signals; dedicated resource circuit means operatively connected with said input/output means and with common resource circuit means for transfer of digital information thereamong and for performing a plurality of data processing tasks on an in response to said digital information when so connected; wherein said common resource circuit means includes storage means for storing said digital information including said received and transmitted information, arithmetic and logic circuit means for performing logical and other manipulative operations on said digital information, timing and control circuit means connected to receive said major cycle timing signals for providing timing and control signals throughout said data processing system, and processor control means for selectively operatively connecting said dedicated resource circuit means with said common resource circuit means to perform said data processing tasks; the improvement being characterized by: a. said basic timing circuit means comprising means for generating said major cycle timing signals having a duration of one or more storage reference cycle times of said data processing system up to that period of time required by said system to execute an instruction; b. said dedicated resource circuit means comprising a plurality of register groups each being operatively connectable one at a time with said common resource circuit means for independently operatively executing when so connected a different one of said plurality of data processing tasks on said major cycle time period basis; c. said data processing system including means for producing resource utilization request signals for each of said register groups and common resource circuit means combinations, in response to the individual task execution needs; and d. said processor control means including resource allocation circuit means responsive to said major cycle timing signals and operatively connected to receive said plurality of resouce utilization request signals for operatively connecting with said common resource circuit means selected ones of said plurality of register groups on said major cycle time period basis according to said resource utilization request signals.

Claim 25

In a reconfigured data processing system having: input/output means for receiving and transmitting information from and to external sources; basic timing circuit means for generating major cycle timing signals; dedicated resource circuit means operatively connected with said input/output means and with common resource circuit means for transfer of digital information thereamong and for performing a plurality of data processing tasks on an in response to said digital information when so connected; wherein said common resource circuit means includes storage means for storing said digital information including said received and transmitted information, arithmetic and logic circuit means for performing logical and other manipulative operations on said digital information, timing and control circuit means connected to receive said major cycle timing signals for providing timing and control signals throughout said data processing system, and processor control means for selectively operatively connecting said dedicated resource circuit means with said common resource circuit means to perform said data processing tasks; the improvement being characterized by: a. said basic timing circuit means comprising means for generating said major cycle timing signals having a duration of one or more storage reference cycle times of said data processing system up to that period of time required by said system to execute an instruction; b. said dedicated resource circuit means comprising a plurality of register groups each being operatively connectable one at a time with said common resource circuit means for independently operatively executing when so connected a different one of said plurality of data processing tasks on said major cycle time period basis; c. said data processing system including means for producing resource utilization request signals for each of said register groups and common resource circuit means combinations, in response to the individual task execution needs; and d. said processor control means including resource allocation circuit means responsive to said major cycle timing signals and operatively connected to receive said plurality of resouce utilization request signals for operatively connecting with said common resource circuit means selected ones of said plurality of register groups on said major cycle time period basis according to said resource utilization request signals.

Claim 26

An improved reconfigured data processing system according to claim 6, wherein said resource allocation circuit means include priority circuit means for determining the order in which said plurality of register groups are operatively connected with said common resource circuit means, wherein said priority circuit means includes means connected to receive said plurality of resource utilization request signals for assigning priority weightings thereto according to a predetermined priority schedule.

Claim 27

An improved reconfigured data processing system according to claim 7, wherein said input/output means includes means for providing priority override signals in response to said data processing task executions, and wherein said priority circuit means includes means connected to receive said priority override request signals and being responsive thereto for excluding those ones of said request signals which are of a non-time dependent nature.

Claim 28

A reconfigured data processing system, comprising: a. input/output means for receiving an transmitting information from and to external sources; b. storage means for storing digital information including said received and transmitted information; and c. data handling circuit means operatively connecting said input/output means with said storage means for handling said digital information said data handling circuit means including a central processor comprising:

Claim 29

A reconfigured data processing system, comprising: a. input/output means for receiving an transmitting information from and to external sources; b. storage means for storing digital information including said received and transmitted information; and c. data handling circuit means operatively connecting said input/output means with said storage means for handling said digital information said data handling circuit means including a central processor comprising:

Claim 30

An improved data processing system, comprising: a. input/output means for receiving and transmitting information from and to external sources; b. storage means for storing digital information including said received and transmitted information; c. data handling circuit means operatively connecting said input/output means with said storage means for handling said digital information, said data handling circuit means including a central processor, comprising:

Claim 31

An improved data processing system, comprising: a. input/output means for receiving and transmitting information from and to external sources; b. storage means for storing digital information including said received and transmitted information; c. data handling circuit means operatively connecting said input/output means with said storage means for handling said digital information, said data handling circuit means including a central processor, comprising:

Claim 32

An improved data processing system according to claim 10, wherein each of said plurality of dedicated register groups is operatively identifiable with a different one of said plurality of data processing means, and wherein said resource allocation circuit means includes means responsive to said major cycle timing signals for activating on said major cycle time period basis a selected one of said plurality of data processing means by operatively connecting that one of said dedicated register groups which is operatively identified with said selEcted data processing means, with said shared arithmetic and logic circuit means, said storage means and said timing and control circuit means.

Claim 33

An improved data processing system according to claim 11, wherein said resource allocation circuit means includes inhibiting circuit means for preventing the activation of a same one of said plurality of data processing means on any two successive major cycle time periods.

Claim 34

An improved data processing system according to claim 11, wherein each of said plurality of data processing means is connected for autonomous operation with respect to the remaining plurality of said data processing means in performing its said data processing tasks.

Claim 35

An improved data processing system according to claim 13, wherein said central processor includes cross-reference circuit means operatively connected with said resource allocation circuit means and with said plurality of data processing means for enabling at least one of said data processing means when activated to operatively reference a different one of said plurality of data processing means such that said autonomous operation of said activated data processing means is preserved.

Claim 36

An improved data processing system according to claim 10, including means operatively connecting at least one of said plurality of data processing means with said inout/output means and with said storage means for transmitting said digital information therebetween.

Claim 37

An improved data processing system according to claim 10, wherein said plurality of data processing means include means for producing resource utilization request signals indicative of said activation requirements of said data processing means; wherein said resource allocation circuit means includes priority determining circuit means connected to receive said resource utilization request output signals, being responsive thereto and to said major cycle timing signals for providing priority output signals on said major cycle time period basis, indicating according to a predetermined priority schedule, that data processing means having the highest activation priority for the performance of its said data processing task; and wherein said resource allocation circuit means further includes activating circuit means operatively connected to receive said priority output signals, being responsive thereto and to said major cycle timing signals for selectively activating said data processing means on said major cycle time period basis.

Claim 38

An improved data processing system according to claim 16, wherein said means for producing said resource utilization request signals comprises a plurality of separate utilization request signal producing means one each of said separate utilization request signal producing means being operatively connected with a different one of each of said plurality of data processing means, each of said separate utilization request signal producing means being operative to produce said resource utilization request signals in real time and responsive to real time execution requirements of that data processing task currently being executed by its associated data processing means.

Claim 39

An improved data processing system according to claim 10, wherein said digital information includes at least one coded instruction program, and wherein said plurality of data processing means, when actively performing said data processing tasks, includes means for executing instructions of said coded instruction program.

Claim 40

An improved data processing system according to claim 18, wherein said central processor includes cross-reference circuit means operatively connected with said resource allocation circuit means and with one or more of said plurality of data processing means for enabling a first of said data processing means so connected to said cross-reference circuit means to address registers within said dedicated register group of a second one of said plurality of data processing means.

Claim 41

An improved dAta processing system according to claim 19, wherein one of said plurality of data processing means which is operatively connected with said cross-reference circuit means includes means for performing executive data processing tasks.